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Enhanced GSM Processor
AD6426
CHANNEL CODEC VOICEBAND / BASEBAND CODEC INTERFACE TEST INTERFACE
Preliminary Technical Information
FEATURES Complete Single Chip GSM Processor Channel Codec Subsystem including Channel Coder/Decoder Interleaver/De-interleaver Encryption/Decryption Control Processor Subsystem including 16-bit Control Processor (H8/300H) Parallel and Serial Display Interface Keypad Interface EEPROM Interface SIM-Interface Universal System Connector Interface Interface to AD6425 Control of Radio Subsystem Programmable backlight duty cycle Real Time Clock with Alarm Battery ID Chip Interface DSP Subsystem including 16-bit DSP with ROM coded firmware for Full rate Speech Encoding/Decoding (GSM 06.10) Enhanced Full Rate Speech Encoding/Decoding (GSM 06.60) Equalization with 16-state Viterbi (Soft Decision) DTMF and Call Progress Tone Generation Power Management of Mobile Radio Slow Clocking scheme for low Idle Mode current Ultra Low Power Design On-chip GSM Data Services up to 14.4 kbit/s JTAG Test Interface 2.4V to 3.3V Operating Voltage 144-Lead LQFP and 144-Lead PBGA packages APPLICATIONS GSM 900 / DCS1800 / PCS1900 Mobile Stations (MS) Compliant to Phase 1 and Phase 2 specifications GENERAL DESCRIPTION The AD6426 Enhanced GSM Processor (EGSMP) is the central component of the highly integrated AD20msp425 GSM Chipset. Offering a low total chip count, low bill of materials cost and long talk and standby times, the chipset offers designers a straightforward route to a highly competitive product in the GSM/DCS1800 market. The EGSMP performs all the baseband functions of the Layer 1 processing of the GSM air interface. This includes all data encoding and decoding processes as well as timing and radio sub-system control functions. The EGSMP supports full rate and enhanced full rate speech traffic as well as a full range of data services including F14.4.
UNIVERSAL SYSTEM CONN. INTERFACE
DSP
CHANNEL EQUALIZER
DISPLAY INTERFACE
SIM INTERFACE
RADIO INTERFACE SPEECH CODEC
EEPROM INTERFACE
ACCESSORY INTERFACE
MEMORY INTERFACE
CONTROL PROCESSOR
KEYPAD / BACKLIGHT INTERFACE
Figure 1. Functional Block Diagram In addition, the EGSMP supports both A5/1 and A5/2 encryption algorithms as well as operation in non-encrypted mode. The EGSMP integrates a high performance 16-bit microprocessor (Hitachi H8/300H), that supports all the GSM terminal software, including Layer 1, 2 and 3 of the GSM protocol stack, the MMI and applications software such as data services, test and maintenance. The use of the standard H8 processor allows the use of HIOS, the Hitachi real time kernel, as well as a full range of software development tools including C compilers, debuggers and incircuit emulators. The EGSMP also integrates a high performance 16-bit Digital Signal Processor (DSP), which provides speech transcoding and supports all audio functions in both transmit and receive. In receive it equalizes the received signal using a 16-state (Viterbi) soft decision equalizer. The EGSMP interfaces with all the peripheral sub-systems of the terminal, including the keypad, memories, display driver, SIM, DTE and DTA data services interface and radio. It also has a general purpose interface that can be used to support an external connection to a car kit or battery charger. The EGSMP interfaces with the AD6425 or the AD6421 Voiceband/Baseband Codec through a dedicated serial port. ORDERING GUIDE Model AD6426XST AD6426XB Temperature Range -25C to +85C -25C to +85C Package 144-Lead LQFP 144-Lead PBGA
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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CLKIN OSC13MON OSCIN OSCOUT JTAGEN TCK TMS TDI TDO
AD6426
VCTCXO
SYSTEM CONNECTOR
USCRI USCRX USCTX USCCTS USCRTS GPIO [9:0] GPCS GPPWRCTL SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY EEPROMEN EEPROMDATA EEPROMCLK BACKLIGHT KEYPADROW [5:0] KEYPADCOL [3:0]
JTAG PORT
ACCESSORY
VBC / EVBC AD6421 / 25
CLKOUT VBCRESET ASDO ASOFS ASCLK ASDI MCLK RESET ASDI ASDIFS ASDOFS ASCLK ASDO BSDI BSDIFS BSCLK BSDO BSDOFS MODE VSDO VSDI VSCLK VSFS VSDI VSDO VSCLK VSFS
SIM
EEPROM
BACKLIGHT KEYPAD
ENHANCED GSM PROCESSOR AD6426
BSDO BSOFS BSCLK BSDI BSIFS
FLASH ROM
FLASHPWD ROMCS ADD [20:0] DATA [15:0] RAMCS
SRAM RD WR HWR LWR DISPLAY LCDCTL DISPLAYCS POWER SUBSYSTEM
RXON TXON RXON TXENABLE TXPHASE TXPA CALIBRATERADIO RADIOPWRCTL SYNTHEN0 SYNTHEN1 SYNTHDATA SYNTHCLK AGCA AGCB
VDDRTC PWRON
RADIO
IRQ6 RESET BOOTCODE VDD(10) GND(10)
Figure 2. External Interfaces of the AD6426
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Table of Contents
GENERAL DESCRIPTION ...................................................1 PIN FUNCTIONALITY ( Normal Mode) ...............................4 OVERVIEW..........................................................................7 FUNCTIONAL PARTITIONING ...........................................7 Channel Codec Sub-System ...............................................7 Processor Sub-System ........................................................8 DSP Sub-System................................................................8 Speech Transcoding .......................................................8 Equalization...................................................................8 Audio Control ................................................................8 Tone Generation ............................................................8 Automatic Frequency Control (AFC) ..............................8 Automatic Gain Control (AGC)......................................8 REGISTERS..........................................................................9 GENERAL CONTROL........................................................14 Clocks .............................................................................14 Slow Clocking .................................................................14 Real Time Clock and Alarm.............................................14 Reset ...............................................................................15 Interrupts .........................................................................15 NMI.................................................................................15 Wait ................................................................................16 Automatic Booting...........................................................16 Power Control..................................................................16 INTERFACES .....................................................................16 Memory Interface.............................................................16 EEPROM Interface ..........................................................16 SIM Interface...................................................................17 Accessory Interface ..........................................................17 Universal System Connector Interface ..............................18 Operating modes of the USC............................................18 Buffered UART Mode (Booting/Data Services)................18 Keypad / Backlight / Display Interface .............................19 Battery ID Interface..........................................................20 EVBC Interface ...............................................................20 Radio Interface ................................................................22 Dual Band Control .......................................................22 Tx Timing Control .......................................................23 Rx Timing Control .......................................................24 Synthesizer Control ......................................................24 AGC Control................................................................25 TEST INTERFACE .............................................................27 JTAG Port....................................................................27 Debug Port Interface ....................................................29 MODES OF OPERATION...................................................29 Normal Mode (Mode A) ..................................................29 Emulation Mode (Mode D) ..............................................29 FEATURE MODES.............................................................30 DAI Mode........................................................................30 High Speed Logging.........................................................30 SPECIFICATIONS ..............................................................32 General............................................................................32 ABSOLUTE MAXIMUM RATINGS ...............................32 TIMING CHARACTERISTICS............................................33 Clocks .............................................................................33
AD6426
Memory Interface.............................................................34 Radio Interface ................................................................35 High Speed Logging Interface ..........................................36 Data Interface ..................................................................37 Test Interface...................................................................38 EVBC Interface ASPORT ................................................39 EVBC Interface BSPORT ................................................40 EVBC Interface VSPORT ................................................41 Parallel Display Interface .................................................42 Serial Display Interface....................................................43 PACKAGING......................................................................44 LQFP Pin Locations.........................................................44 PBGA Pin Locations ........................................................45 LQFP Outline Dimensions ...............................................47 PBGA Outline Dimensions ..............................................48
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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PIN FUNCTIONALITY ( Normal Mode) Group General Pin Name CLKIN RESET IRQ6 OSC13MON BOOTCODE VDD GND Memory Interface ADD19 : 0 GPO10 DATA15 : 0 RD HWR LWR WR FLASHPWD RAMCS ROMCS SIM Interface SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY EEPRROM Interface Display / Backlight / Keypad Interface EEPROMDATA EEPROMCLK EEPROMEN DISPLAYCS LCDCTL BACKLIGHT KEYPADROW5 : 0 KEYPADCOL3 : 0 Pins 1 1 1 1 1 10 10 20 1 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 4 O O/O I/O O O O O O/I/ O O O I/ I/O O I O O O/ I/O O I/O O O O O O I O I/O I I I/I O I Default / Alternative Function(s) * 13 MHz Clock Input Reset input
AD6426
Interrupt Request # 6 / Non-Maskable Interrupt (NMI) * 13 MHz Oscillator Power Control Signal Boot Code Enable Supply Voltage Ground Processor Address Bus General Purpose Output 10 / Address (20) * Processor Data Bus Processor Read Strobe Processor High Write Strobe / Upper Byte Strobe Processor Low Write Strobe / Lower Byte Strobe Processor Write Strobe FLASH Power Down / WAIT / General Purpose Output 11* External RAM Chip Select External ROM Chip Select SIM Card Detect / General Purpose I/O 16 * SIM Data Output SIM Data Input SIM Clock SIM Reset SIM Program Enable / General Purpose I/O 15 * SIM Supply Enable EEPROM Data EEPROM Clock / High Speed Logger Clock EEPROM Enable / High Speed Logger Frame Sync Display Controller Chip Select / Chip Enable LCD Control / Serial Display Data Output Backlight Control Keypad Row Inputs Keypad Column Strobes (open drain, pull low)
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Pin Functionality ( NORMAL MODE) Group EVBC Interface ASPORT Pin Name CLKOUT EVBCRESET ASDO ASOFS ASCLK ASDI BSPORT BSDO BSOFS BSCLK BSDI BSIFS VSPORT VSDO VSDI VSCLK VSFS Radio Interface RXON TXPHASE TXENABLE TXPA CALIBRATERADIO RADIOPWRCTL SYNTHEN0 SYNTHEN1 SYNTHDATA SYNTHCLK AGCA AGCB Universal System Connector Interface USCRI USCRX USCTX USCCTS USCRTS Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O O O O O O I O O I I I O I I I O O O O/O O/O O O O O O O O 1/O I O I/O O Default / Alternative Function(s) * Clock Output to EVBC EVBC Reset Output (also for Display reset) EVBC Auxiliary Serial Port Data Output
AD6426
EVBC Auxiliary Serial Port Output Framing Signal EVBC Auxiliary Serial Port Clock Output EVBC Auxiliary Serial Port Data Input EVBC Baseband Serial Port Data Output EVBC Baseband Serial Port Output Framing Signal EVBC Baseband Serial Port Clock Input EVBC Baseband Serial Port Data Input EVBC Baseband Serial Port Input Framing Signal EVBC Voiceband Serial Port Data Output EVBC Voiceband Serial Port Data Input EVBC Voiceband Serial Port Clock Input EVBC Voiceband Serial Port Framing Signal Receiver On Switches between Rx and Tx Transmit Enable / General Purpose Output 14 * Power Amplifier Enable / General Purpose Output 12 * Radio Calibration / General Purpose Output 13 * Radio Power-Down Control Synthesizer 1 Enable Synthesizer 2 Enable / General Purpose Output 17 * RF Serial Port Data RF Serial Port Clock AGC Gain Select / General Purpose Output 18 AGC Gain Select / General Purpose Output 19 USC Ring Indicator / Serial Clock / GPO20 USC Receive Data USC Transmit Data / Baseband Serial Port Data Input USC Clear to Send / Serial Frame Sync / GPI22 USC Ready to Send / GPO21
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Pin Functionality ( NORMAL MODE) Group Accessory Interface Pin Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPCS Real Time Clock Interface Test Interface OSCIN OSCOUT VDDRTC PWRON JTAGEN TCK TMS TDI TDO Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 O I I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O Default / Alternative Function(s) * General Purpose Inputs/Output 0
AD6426
General Purpose Inputs/Output 1 / Radio BANDSELECT1 * General Purpose Inputs/Output 2 / Radio BANDSELECT0 * General Purpose Inputs/Outputs 3 / Serial Display Address Output * General Purpose Inputs/Outputs 4 / Serial Display Clock Output * General Purpose Inputs/Outputs 5 / Battery ID Interface * General Purpose Inputs/Output 6 / VBIAS * General Purpose Inputs/Output 7 / Antenna Select * General Purpose Inputs/Output 8 / DEBUG UART Transmit Data * General Purpose Inputs/Output 9 / DEBUG UART Receive Data * General Purpose Chip Select 32.768 kHz Crystal Input 32.768 kHz Oscillator Output and Feedback to Crystal RTC Supply Voltage Power ON/OFF Control JTAG Enable JTAG Test Clock / HSL Data 0 JTAG Test Mode Select / HSL Data 1 / DAI Reset JTAG Test Data Input / HSL Data 3 / DAI Data 1 JTAG Test Data Output / HSL Data 2 / DAI Data 0
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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OVERVIEW The GSM air interface has been formulated to provide high quality digital mobile communication. As well as supporting the traffic channels (speech and/or data), the air interface specifies a number of signaling channels that are used for call set up and communications between the network infrastructure and the mobile. These signaling channels provide the mobile specific features such as handover, as well as a number of other intelligent features. The GSM system closely follows the OSI 7-layer model for communications. Specifically, GSM defines Layers 1, 2 and 3 of the protocols. The lowest level being Layer 1, or the Physical Layer. It is this part of the network processing for which the EGSMP is responsible, performing some of the Layer 1 functions in dedicated hardware for minimum power consumption and some in software for increased flexibility. Layer 1 covers those signal processing functions required to format the speech/data for transmission on the physical medium. Data must be structured to allow for identification, recovery and error correction so that the information can be supplied error free to the layer 2 sub-systems and to the traffic sources. In addition, the physical layer processing includes the timing of both transmit and receive data, the encryption of data for security purposes and the control of the Radio subsystem to provide timing and to optimize the radio frequency characteristics. An object code license to Layer 1 software is supplied with the AD20msp425 chipset. FUNCTIONAL PARTITIONING This datasheet gives only an overview about the functionality of the EGSMP. The EGSMP consists of three main elements; the Channel Codec and the Control Processor Sub-System including several interfaces and the DSP as shown in Figure 1. The Channel Codec is responsible for the Layer 1 channel coding and decoding of traffic and control information. The Processor Sub-system supports the software functions of the protocol stack and interfaces with the bus peripheral subsystems of the terminal. The DSP performs the channel equalization and speech transcoding. Channel Codec Sub-System The Channel Codec processes data from two principal sources; traffic and signaling. The former is normally continuous and the latter determined on demand. Traffic comes in two forms; speech and user data. The various traffic sources and the signaling sources are all processed differently at the physical layer. Speech traffic data is supplied by the speech transcoder and the remaining data types are sourced from the Control Processor and interfaced via a dedicated data interface. The Channel Codec subsystem functional block diagram is shown in Figure 3.
ENCODE INTERLEAVE ENCRYPT
AD6426
DSP INTERFACE
VBC INTERFACE
DECODE
DEINTERLEAVE
DECRYPT
REGISTERS H8 INTERFACE RADIO / SYNTHESIZER TIMING AND CONTROL
TEST INTERFACE
Figure 3. Channel Codec Subsystem The transmit and receive functions of the Channel Codec are timed by an internal timebase that maintains accurate timing of all sub-systems. This timebase is aligned with the on-air receive signal and all system control signals, both internal and external, are derived from it. The physical layer processing can be divided into 4 phases, two each for up- and downlink. The data in the transmit path undergoes an ENCODE phase and then a TRANSMIT phase. Similarly, data in the downlink path is termed the receive data and it undergoes a RECEIVE phase followed by a DECODE phase. The buffer between the ENCODE and TRANSMIT functions is the INTERLEAVE module that holds the data and permits the building of the transmit burst structure. Similarly the DEINTERLEAVE module forms the buffer between the RECEIVE and the DECODE processes. Each of these four phases is controlled explicitly by the Control Processor via control registers that define the mode of operation of each sub-module and the data source they should process. Typically these control values are updated every TDMA frame in response to interrupts from the internal timebase. The ENCODE process involves the incorporation of error protection codes. All data is sourced in packets and two forms of error coding applied; block coding (parity or Fire code) and convolution coding. The resultant data block is then written to the INTERLEAVE module where it is buffered in a RAM. Data is read from the interleave buffer memories contiguously but written in non-contiguous manner, thereby implementing the interleaving function. The TRANSMIT process uses a different time structure now associated with the on-air TDMA structure. The data is read from the INTERLEAVE module and formatted into bursts with the requisite timing. This involves adding fixed patterns such as the tail bits and training sequence code. The resultant burst is written to the external Baseband Converter where the modulation is performed and the output timed to the system timebase before transmission.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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A feature of the GSM system is the application, as part of the TRANSMIT process, of data encryption for the purpose of link security. After the INTERLEAVE module the data may be encrypted using the prescribed A5/1 or A5/2 encryption algorithm. The RECEIVE function requires unmodulated baseband data from the equalizer. As necessary the data is decrypted and written to the DEINTERLEAVE module. This is conducted at TDMA frame rate, although precise timing is not necessary at this stage. The DECODING process reads data from the DEINTERLEAVE module, inverting the interleave algorithm and decodes the error control codes, correcting and flagging errors as appropriate. The data also includes a measure of confidence expressed as two additional bits per received symbol. These are used in the convolution decoder to improve the error decoding performance. The resultant data is then presented to the original sources as determined by the control programming. The Channel Codec interfaces with the speech transcoder for speech traffic data and with an equalizer for recovered receive data. In the AD6426 the equalizer and speech transcoder are implemented in the DSP. Processor Sub-System The Processor Sub-System consists of a high performance 16bit microcontroller together with a selection of peripheral elements. The processor is a version of the Hitachi H8/300H that has been developed to support GSM applications and which is well suited to support the Protocol Stack and Application Layer software. DSP Sub-System The DSP Sub-System consists of a high performance 16-bit digital signal processor (DSP) with integrated RAM and ROM memories. The DSP performs two major tasks: speech transcoding and channel equalization. Additionally several support functions are performed by the DSP. The instruction code, which advises the DSP to perform these tasks, is stored in the internal ROM. The DSP sub-system is completely selfcontained, no external memory or user-programming is necessary. Speech Transcoding In Full Rate mode the DSP receives the speech data stream from the EVBC and encodes the data from 104 kbit/s to 13 kbit/s. The algorithm used is Regular Pulse Excitation, with Long Term Prediction (RPE-LTP) as specified in the 06-series GSM Recommendations. In Enhanced Full Rate mode, the DSP encodes the 104 kbit/s speech data into 12.2 kbit/s (speech) +0.8 kbit/s (CRC and repetition bits) as additionally specified in the Phase 2 version of the 06-series GSM Recommendations. In both modes, the DSP also performs the appropriate voice activity detection and discontinuous transmission (VAD/DTX) functions.
AD6426
Alternatively the DSP receives encoded speech data from the channel codec sub-system including the Bad Frame Indicator (BFI). The Speech decoder supports a Comfort Noise Insertion (CNI) function that inserts a predefined silence descriptor into the decoding process. The resulting data, at 104 kbit/s, is transferred to the EVBC. Equalization The Equalizer recovers and demodulates the received signal and establishes local timing and frequency references for the mobile terminal as well as RSSI calculation. The equalization algorithm is a version of the Maximum Likelihood Sequence Estimation (MLSE) using the Viterbi algorithm. Two confidence bits per symbol provide additional information about the accuracy of each decision to the channel codec's convolutional decoder. The equalizer outputs a sequence of bits including the confidence bits to the channel codec subsystem. Audio Control The DSP subsystem is also responsible for the control of the audio path. The EVBC provides two audio inputs and two audio outputs, as well as a separate buzzer output, which are switched and controlled by the DSP. Furthermore the EVBC provides for variable gain and sensitivity which is also controlled by the DSP under command of the Layer 1 software. Tone Generation All alert signals are generated by the DSP and output to the EVBC. These alerts can be used for the buzzer or for the earpiece. The tones used for alert signals can be fully defined by the user by means of a description which provides all the parameters required such as frequency content and duration of components of the tone. The tone descriptions are provided by the Layer 1 software. Automatic Frequency Control (AFC) The detection of the frequency correction burst provides the frequency offset between the mobile terminal and the received signal. This measure is supplied to the Layer 1 software which then requests a correction of the master clock oscillator frequency via the AFC-DAC in the EVBC. In order to do so the Layer 1 software includes a transfer function for the oscillator frequency against the voltage applied. The DSP provides the measurements for the AFC. Automatic Gain Control (AGC) The DSP is also responsible for making measurements of the power in the received signal. This is used for a number of functions including RSSI measurement, adjacent channel monitoring and AGC. The Layer 1 software passes the requested gain level to the DSP, which then analyzes the received signal and generates an AGC control signal. Depending on the radio architecture, this control signal will be used in digital form or, converted by the AD6425 in analog form.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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REGISTERS The AD6426 contains 88 Channel Codec Control Registers, 69 H8 Peripheral Registers mapped into the Channel Codec address space starting at 8000h. All registers are normally accessed by the Layer 1 software provided with the AD20msp425 chipset. The user is not expected to read or write to any registers other than through the Layer 1 software. Therefore only a limited description of these registers is given here to ease the understanding of the functional behavior of the AD6426. Only registers which can be modified or monitored by the user under control of the Layer 1 software are shown. The Channel Codec Control Registers are listed in Table 1, and the H8 Peripheral Control Registers in Table 3 A description of the Channel Codec Control Register contents is shown in Table 2, and of the H8 Peripheral Registers in Table 4. Table 1. CC Control Registers
AD6426
Address
72 73 74 75 76 77 78 79 88 48 H 49 H 4A H 4B H 4C H 4D H 4E H 4F H 58 H
Name
SYNTHESIZER PROGRAM TXPA OFFSET 1 TXPA OFFSET 2 TXPA WIDTH 1 TXPA WIDTH 2 IRQ ENABLE IRQ LATCH CC GPIO ccGPO R/W R/W R/W R/W R/W R/W RMW R/W R/W
Address
0 2 4 5 6 7 8 9 10 28 29 30 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 00 H 02 H 04 H 05 H 06 H 07 H 08 H 09 H 0A H 1C H 1D H 1E H 23 H 25 H 26 H 27 H 28 H 29 H 2A H 2B H 2C H 2D H 2E H 2F H 30 H 31 H 32 H 33 H
Name
SYSTEM RADIO CONTROL BSIC TSC TRAFFIC MODE DAI EEPROM KEYPAD COLUMN KEYPAD ROW EVBC SERIAL 1 EVBC SERIAL 2 EVBC IF CONTROL RESET SYNTH BIT COUNT SYNTH CONTROL ERROR COUNT SYNTHESIZER 1 SYNTHESIZER 2 SYNTHESIZER 3 SYNTHESIZER 4 POWER CONTROL INT POWER CONTROL EXTERNAL SWRESET 1 SWRESET 2 INTERRUPT COUNTER BBC TX ADDRESS BACKLIGHT VERSION CONTROL R/W R/W R/W R/W R/W R/W R/W R/W RD RMW RMW R/W R/W R/W R/W RMW WR WR WR WR R/W R/W R/W R/W R/W R/W WR RD
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Table 2. CC Control Register Contents
AD6426
3
Calibrate Radio Tx PHASE Enable
#
0 2 4 5 6 7 8 9 10 28 29 30 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 72 73 74 75 76 77 78 79 88
7
Autocalibrate Tx Monitor Enable
6
Tx Phase Polarity
5
Backlight 1 Rx Radio Control Polarity
4
Test Data Enable Tx Radio Control Polarity
2
Encryption Type Monitor Enable
1
Encrypt Key Load Receive Enable Training Sequence Code
0
Transmit Enable
Base Station Identity Code TxPA Polarity INT COUNT[8] BAND ENABLE OCE OVERRIDE Interrupt Counter Override NMI Select EEPROM Data Output Enable Keypad Row EVBC Serial Port ( 15 : 8 ) EVBC Serial Port ( 7 : 0 ) Tx Data Delay EVBC Reset Isolate Synthesizer Synthesizer Enable Polarity Config. Dynam. Synthesizer Synthesizer Enable Type Synthesizer Interface active Synthesizer Clock Polarity Error Count Synthesizer (31: 24) Synthesizer (23: 16) Synthesizer (15: 8) Synthesizer (7: 0) Backlight Duty Cycle Coprocessor Power Control Output Clock Enable GP Power Control Encryption SW-Reset INT CNT RST Decode SW-Reset EVBC Tx Address Modulate 1 Version Disable Synth.1 Disable Synth. 0 Synt. Enable Sel. Synt. Mode Pin Mode TD ( 9 : 8 ) TD ( 7 : 0 ) TW ( 9 : 8 ) TW ( 7 : 0 ) GPO11 Data GPO11 Select IRQ5 Enable IRQ5 active GPIO9 OP En GPO19 Sel GPO18 Sel IRQ4 Enable IRQ4 active GPIO8 OP En GPO17 Sel IRQ3 Enable IRQ3 active IRQ2 Enable IRQ2 active GPIO9 Data GPO19 GPO18 GPIO8 Data GPO17 FLASHPWD dis. NMI Edge Pol. Backlight LED Control Synth. Interface Power Enable DSP Power Control EVBC Interface SW-Reset Deinterleave SW-Reset Interrupt Counter EVBC Read DSP Interface Power Enable Radio Power Control DSP Interface SW-Reset interleave SW-Reset Synthes. Interface SW-Reset Encode SW-Reset Encryption Power Enable DSP Reset Synthesizer Bit Count Synthesizer Load Dynamic 1 Synthesizer Load Dynamic 2 Synthesizer Clock EVBC Rx-Buff. full EVBC Tx-Buf.empty CC Reset Autocalibration Type GPO10 Data Traffic Frame Enable GPO10 Select EERPOM Clock Decryption Enable Data Ser. Select EEPROM Enable Encryption Enable DAIRESET EERPOM Data
Keypad Column
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Table 3. H8 Peripheral Control Registers
AD6426
Address
64/65 8040/1h 8042h 8043h 8044h 8045h 8048h 8050h 8051h 8052h 8054h 8055h 8060h 8061h 8062h 8063h 8064h 8065h 8066h 8067h 8068h 8069h 8074h 66
Name
DISPDDR DISPCR DDOR DDIR DRR WDTR MEM IF PERST PERCR TAR PERCLK RTCTR1 RTCTR2 RTCTR3 RTCTR4 RTCTR5 RTCAR1 RTCAR2 RTCAR3 RTCCR RTCSRZ SERDISPLAY/NMI W R/W W R R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address
0 1 2 3 4 5 6 10 10 10 11 11 12 12 13 14 15 16 17 18 18 19 26 27 28 29 32 32 32 33 33 34 35 36 37 38 39 48 49 50 51 52 53 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8010h 8010h 8010h 8011h 8011h 8012h 8012h 8013h 8014h 8015h 8016h 8017h 8018h 8018h 8019H 801AH 801BH 801CH 801Dh 8020h 8020h 8020h 8021h 8021h 8022h 8023h 8024h 8025h 8026h 8027h 8030h 8031h 8032h 8033h 8034h 8035h
Name
SMSMR SMBRR SMSCR SMDR SMSSR SMDR SMSCMR BUFRBR BUFTHR BUFDLL BUFIER BUFDLM BUFIIR BUFFCR BUFLCR BUFMCR BUFLSR BUFMSR BUFSCR UIBRBR UIBTHR UIBSSR UIBER UIBTSR UIBTLR UIBBLR FIXRBR FIXTHR FIXDLL FIXIER FIXDLM FIXIIR FIXLCR FIXMCR FIXLSR FIXMSR FIXSCR SCCR SPSSR SDIR1 (MS) SDIR0 (LS) SDOR1 (MS) SDOR0 (LS) R/W R/W R/W W R/W R R/W R W R/W R/W R/W R W R/W R/W R/W R/W R/W R W R/W R R R/W R R W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R W W
67 68 69 72 80 81 82 84 85 96 97 98 99 100 101 102 103 104 105 106
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Table 4. H8 Peripheral Register Contents
AD6426
4
ODD
#
0 1 2 3 4 5 6 10 10 10 11 11 12 12 13 14 15 16 17 18 18 19 26 27 28 29 32 32 32 33 33 34 35 36 37 38 39 48 49 50 51 52 53 64/65
7
6
5
3
2
1
0
TIE TDRE
RIE RDRF
TE ORER
RE Transmit[7:0] ERS Receive[7:0] RxData[7:0] TxData[7:0] BRR[7:0]
AE PER
BRR[3:0] DATEN CLKPOL TEND
CLKEN
EDSSI BRR[15:8] FIFO ST FIFO ST RxLevel[1:0] DLAB SET BRK Error Rx FIFO DCD TEMT RI DMA Parity EN Out2 Framing Error DDCD
ELSI InterruptID[2:0] TX FIFO Stop Bits Out1 Parity Error TERI
ETBEI
ERBFI
Stick Par. THRE DSR
Ev. Parity Loop Break Interrupt CTS SCR[7:0] RxData[7:0] TxData[7:0] RE
Int Pend RX FIFO FIFO EN WLS[1:0] RTS DTR Overrun Error Data Ready DDSR DCTS
TE Tx Trigger Level [3:0] Chars in TX Buffer [3:0]
FE MODEM
MRESET PE TX Level
UIB Enable PROC BI OE RX Time RX Level Rx Trigger Level [3:0] Chars in Rx Buffer [3:0]
RxData[7:0] TxData[7:0] BRR[7:0] EDSSI BRR[15:8] FIFO ST DLAB Error Rx FIFO DCD TEST FIFO ST SET BRK TEMT RI RX MODE SDORIE Stick Par. THRE DSR CLOCK SDIROE IE InterruptID[2:0] Ev. Parity Parity EN Loop Out2 Break Interrupt Framing Error CTS DDCD SCR[7:0] TX ENABLE CROSSPOINT SWITCH SDIRIE Receive[15:8] Receive[7:0] Transmit[15:8] Transmit[7:0] Data[7:0] Int Pend Stop Bits Out1 Parity Error TERI UCONN SWITCH SDOR EMT R WLS[1:0] RTS Overrun Error DDSR R/W SDIR OE SDIR FULL R/W DTR Data Ready DCTS ELSI ETBEI ERBFI
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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H8 Peripheral Register Contents (Continued)
AD6426
4 3 2
DISP CLKEN
#
66 67 68 69 72 80 81 82 84 85 96 97 98 99 100 101 102 103 104 105 106
7
6
5
1
CLK FREQ
0
DDREMT
TEST CLK WDT INT WDT IE
Unused RTC INT RTC IE
Unused KEYINT KEY IE USCCLK EN
INTEN INT
TIMWEN TIMER
ALAWEN ALARM TXENABLE NMI
SDISP POL Transmit Data [7:0] Receive Data [7:0] Reset Data [7:0] WDT[7:0] UART SEL DALLAS EN DALLAS INT FA INT DALLAS IE FA IE Test Key[7:0] BUCLK EN FUCLK EN TR[1] TR[2] TR[3] TR[4] TR[5] AR[1] AR[2] AR[3] PWRUEN AGCENN APWRUP SERDISP MODE
RAM SEL7 UA INT UA IE
DISP SSINT SS IE DSPPLL[2:0]
SRAM16 MONINT MONIE
FBENN OSCFAIL
Unused 32K PRESENT
Unused TESTOUT
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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GENERAL CONTROL Clocks Clock Input The AD6426 requires a single 13 MHz, low level clock signal, which has to be provided at the pin CLKIN. For proper operation a signal level of 250 mVPP minimum is required. This feature eases system design and reduces the need for external clock buffering. Only minimal external components are required as shown in Figure 4. The internal clock buffer can accept any regular waveform as long as it can find voltage points in the signal, for which a 50% duty cycle can be determined. This condition is met for sinewaves, triangles, or slew-limited square waves. Dedicated circuitry searches for these points and generates the respective bias voltage internally. The external capacitor (1nF) decouples the bias voltage of the clock signal generated by the oscillator from the internally generated bias voltage of the clock buffer circuitry. The LC-filter shown is optional. It ensures, that the input signal is "well behaved" and sinusoidal. Additionally it filters out harmonics and noise, that may be on top of the pure 13 MHz signal.
Optional 13 MHz Filter
2.2 H 1nF
CLKIN
AD6426
under all circumstances. The active-high OSC13MON output is prevented from becoming inactive if the 32.768kHz signal is not present. The following table describes the functionality of the relevant pins. Name OSCIN OSCOUT OSC13MON PWRON I/O I O O O Function 32.768kHz Crystal Input 32.768kHz Oscillator Output 13 MHz Oscillator Power Control Power ON/OFF Control
The following table lists the recommended specification for a 32kHz crystal. Parameter ESR Shunt Capacitance Load Capacitance Turnover Temperature (To) Parabolic Curvature Constant (K) 6 12.5 25 0.040 Min Typ Max 50 2 30 Units k pF pF C ppm/C
13 MHz VCTCXO
OUT
AD6422
68 pF
Figure 4. Clock Input Circuitry Clock Output The input clock drives both the H8 and the Channel Codec directly. A gated version, controlled by the Output Clock Enable flag in CC Control Register 45, drives the CLKOUT pin of the EVBC interface. The stand-by state of CLKOUT is logic zero. The CLKOUT output will be active on reset. Slow Clocking To reduce power consumption of AD20msp425 solutions, a new slow clocking scheme has been designed into the AD6426. This scheme allows the VCTCXO to be powered down between paging blocks during Idle Mode and for a 32.768kHz oscillator to keep the time reference during this period. Only a common 32.768kHz watch crystal is required to take advantage of this scheme. As in previous generations, power consumption is also kept to a minimum using asynchronous design techniques and by stopping all unnecessary clocks. Layer 1 software and logic built into the AD6426 are responsible for maintaining synchronization and calibration of the slow clock and ensure the validity of the time reference
Real Time Clock and Alarm The AD6426 provides a simple Real Time Clock (RTC) using the 32.768kHz clock input. A 40 bit counter allows for more than one year of resolution. The RTC module contains a 32.768kHz on chip oscillator buffer designed for very low power consumption and a set of registers for a timer, alarm, control and status functions. The RTC circuit is supplied by two sources; a VDDRTC supply pin and the main system VDD. It is the handset designer's responsibility to provide suitable switching between the main system VDD and a backup supply to ensure the RTC module is permanently powered. The VDDRTC pin is intended to interface to a backup battery circuit or charge holding network in order for the RTC to maintain timing accuracy when the main battery is removed and the handset is powered down. The user can set an alarm time at which the handset powers up. If an alarm time is set, the current time matches the alarm time, and the power on alarm feature is enabled, the handset is powered up by asserting the PWRON pin for a period of approximately 2 seconds.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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The VDDRTC was designed to interface with either a: * Lithium Battery or * Capacitor in the range of 0.4F (maximum for ~24 hours standby) to 8mF (~30 minutes standby) Reset The AD6426 is reset by setting the RESET pin to GND. This will reset the H8-processor, the Channel Codec, the internal DSP as well as the LCD controller interface and Boot ROM logic. Both the DSP and the Channel Codec will be held in reset until the RESET register is written to by the H8. At least 50 CLKIN cycles must elapse before deasserting the RESET pin and at least a further 100 cycles before writing to the RESET register. For reset at power up, the DSP must be held in reset for at least 2000 clock cycles to enable the internal PLL to lock. The RESET CC Control Register 35 contains the following flags: Bit 3 2 0 Function EVBC Reset DSP Reset Channel Codec Reset
AD6426
The H8 fetches its program start vector from location 0x0000 in segment zero. This can either be from external ROM or internal Boot ROM, depending on the status of the BOOTCODE pin. Interrupts The interrupts are controlled by the two CC Control Registers 77 and 78. These registers only apply to Emulation Mode, in that they define which of the interrupts are able to assert CCIRQ2. Bit 5 4 3 2 Bit 5 4 3 2 IRQ ENABLE CC Control Register 77 IRQ 5 Enable IRQ 4 Enable IRQ 3 Enable IRQ 2 Enable IRQ LATCH CC Control Register 78 IRQ 5 active IRQ 4 active IRQ 3 active IRQ 2 active
Additionally 8 functional modules can be reset under control of the two SWRESET registers: Bit 3 2 1 0 Bit 3 2 1 0 SWRESET 1 CC Control Register 46 Encryption Software Reset EVBC Interface Software Reset DSP Interface Software Reset Synthesizer Interface Software Reset SWRESET 2 CC Control Register 47 Decode Software Reset Deinterleave Software Reset Interleave Software Reset Encode Software Reset
NMI The non-maskable interrupt NMI input of the H8 processor is multiplexed with the IRQ6 pin. IRQ6 is the default function, though asserting the NMI Select flag in CC Control Register 7 will select the NMI function. When not selected, NMI will be tied off high internally, though it remains driven by the JTAG port for test purposes. The signal is programmable to be edge or level sensitive. It defaults to falling edge. The edge polarity can be changed by programming the H8. However, if FLASHPWD is used then the same setting must be applied to CC Control Register 77. The default of zero implies falling edge sensitive. This way NMI going active can correctly deassert FLASHPWD. The NMI can be used for test purposes or user defined features. NMI is capable of bringing the control processor out of software standby mode and therefore suitable for functions such as alarm inputs, power management etc. During manufacture the NMI can be used to trigger special test code. In addition NMI can be generated internally thus freeing up the IRQ6 PIN. In this mode the TXENABLE NMI will occur on the rising edge of the TXENABLE as seen at the pin. The H8 should be set up for a negative edge NMI in this case. Setting bit 5 in the SERDISPLAY/NMI H8 Peripheral Control Register 106 to a ONE enables the TXENABLE NMI. However, the Layer 1 Software must program the external INT pin to INT6 before the register bit is set.
The JTAG circuitry is reset by a power-on reset mechanism. Further resets must be done by asserting the TMS input high for at least five TCK clock cycles. When JTAG compliance is re-enabled, the JTAG is reset forcing the AD6426 into its normal mode of operation, selecting the BYPASS register by default.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Wait The H8 microprocessor WAIT input signal can be controlled externally by programming the FLASHPWD pin to switch to the WAIT input function. Setting the flag FLASHPWD Disable in CC Control Register 77 to 1 and GPO11 Select to 0, transforms the FLASHPWD output pin into a WAIT input pin. External devices driving WAIT must drive high on reset and until the software has changed the FLASHPWD pin to the WAIT function. Automatic Booting To allow download of FLASH memory code into the final system, the AD6426 provides a small dedicated routine to transfer code through the Data Interface into the FLASH memory. This routine is activated by asserting the BOOTCODE pin. Power Control The AD6426 and Layer 1 software is optimized to minimize the mobile radio power consumption in all modes of operation. Two power control registers are dedicated for activating and deactivating functional modules: Bit 2 1 0 Bit 5 4 2 1 POWER CONTROL INTERNAL CC Control Register 44 Synthesizer Interface Power Enable DSP Interface Power Enable Encryption Power Enable POWER CONTROL EXTERNAL CC Control Register 45 Output Clock Enable (will reset to 1) General Purpose Power Control DSP Power Control Radio Power Control
AD6426
Memory Interface The memory interface of the AD6426 serves two purposes. Primarily, it provides the data, address, and control lines for the external memories (RAM and ROM / FLASH Memory). Secondly, the data and address lines are used to interface with the display. The pins of the memory interface are listed in Table 5. Table 5. Memory Interface Name ADD20 : 0 DATA15:0 RD HWR LWR WR RAMCS ROMCS FLASHPWD I/O O I/O O O O O O O O Function Address bus Data bus Read strobe High write strobe / Upper Byte Strobe Low write strobe / Lower Byte Strobe Write Strobe RAM chip select FLASH / ROM chip select FLASH Powerdown
The HWR and LWR pins can be configured to function as UBS and LBS, respectively, by setting the SRAM16 bit (bit 0) of the MEMIF H8 Peripheral Control Register 80. This bit is reset at power-up. When configured as UBS and LBS, these pins facilitate access of 16-bit SRAM in conjunction with the Read/Write Strobes. The pin FLASHPWD is automatically asserted low when the H8 enters the Software Standby Mode, and de-asserted when an interrupt causes the H8 to exit the Software Standby Mode. This allows the use of "deep power down mode" for certain FLASH memories. Also the entire data bus is driven low during software standby mode. EEPROM Interface The AD6426 provides a 3-wire interface to an external EEPROM by using three GPIOs of the control processor. Table 6 shows the functionality of these three pins. Table 6. EEPROM Interface Name EEPROMDATA EEPROMCLK EEPROMEN I/O I/O O O Function EEPROM data EEPROM clock EEPROM enable
INTERFACES The GSM Processor provides eleven external interfaces for dedicated purposes: 1. Memory Interface 2. EEPROM Interface 3. SIM Interface 4. Accessory Interface 5. Universal System Connector Interface 6. Keypad / Backlight / Display Interface 7. Battery ID Interface 8. Voiceband/Baseband Converter (EVBC) Interface 9. Radio Interface 10. Test Interface 11. Debug Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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The EEPROM interface is controlled entirely through software via the EEPROM register. This allows support for every desired timing and protocol. Bit 4 EEPROM CC Control Register 8 EEPROM Data Output Enable when set to 1, the content of bit 0 will be written to the pin. EEPROM Clock Connected to the EEPROMCLK pin EEPROM Enable Connected to the EEPROMENABLE pin EEPROM Data Connected to the EEPROMDATA pin
AD6426
reflects the input pin state when read and writing to GPIOn Data has no effect. When the GPIOn OP Enable flag is set to 1, the GPIOn Data flag returns when read the last value written to it and controls the GPIOn pin when written to it. Additional general purpose inputs and outputs are available under software control. The following pins shown in Table 9 become general purpose inputs/outputs or outputs. Table 9. Additional GPIO / GPO Pins Pin Name SIMCARD SIMPROG ADD20 FLASHPWD TXPA CALIBRATERADIO TXENABLE SYNTHEN1 AGCA AGCB USCRI USCRTS USCCTS I/O I/O I/O O O O O O O O O O O I New Function GPIO16 GPIO15 GPO10 GPO11 GPO12 GPO13 GPO14 GPO17 GPO18 GPO19 GPO20 GPO21 GPI22
2 1 0
SIM Interface The AD6426 allows direct interfacing to the SIM card via a dedicated SIM interface. This interface consists of 7 pins as shown in Table 7. Some applications may not require SIMPROG and SIMCARD; thus SIMPROG and SIMCARD can be re-used as additional general purpose I/O-pins. Table 7. SIM Interface Name SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY I/O I O I O O O O Function SIM card detect SIM data output SIM data input SIM clock SIM reset SIM program enable SIM supply enable
If the pins SIMCARD and SIMPROG are not required in the application, they can be used as additional H8 programmable general purpose inputs or outputs. Setting GPO10 Select (CC Control Register 7) to 1, will transform the pin ADD20 into a general purpose output allowing the pin to be directly controlled via GPO10 Data. By setting GPO11 Select (CC Control Register 77) to 1 and FLASHPWD Disable to 1, the pin FLASHPWD becomes a general purpose output. The pin state is toggled by setting the GPO11 Data flag. To increase the flexibility of the AD6426, three pins in the Radio Interface are multiplexed within GPO functions. The pins multiplexed are: SYNTHEN1, AGCA and AGCB, with the default function being the Radio Interface. The mode of these pins is controlled by the Channel Codec Register ccGPO. The GPO[n]Sel bit selects the function of the pin. Setting GPO[n]Sel to one will enable the pin to be controlled by the GPO[n] bit. The GPO[n]Sel bit will override any other pin function selection.
Accessory Interface The AD6426 provides 12 interface pins listed in Table 8 for control of peripheral devices such as a car kit. However, two general purpose I/O-pins of the Accessory Interface are proposed to be used for additional control of the radio section as described in the Radio Interface chapter. Table 8. Accessory Interface Name GPIO9:0 GPCS I/O I/O O Function General purpose inputs/outputs General purpose chip select
All GPIO pins start up as inputs. GPIO8 and GPIO9 are controlled by flags in CC Control Register 79. When the GPIOn OP Enable flag is set to 0, the GPIOn Data flag
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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To transform the TXPA pin into a general purpose output, set TXPA Width = 0 (CC Control Register 75 and 76), then use TxPA Polarity flag (CC Control Register 6) to toggle pin state. To use the CALIBRATERADIO pin as a general purpose output, set the AUTOCALIBRATE flag to zero and use the CALIBRATERADIO flag to toggle pin state. Universal System Connector Interface A typical GSM handset requires multiple serial connections to provide data during normal phone operation, manufacturing, testing, and debug. In an ideal case many of these functions could be combined into a single multi-purpose system connector. For example, the USC port can be used for: Operating modes of the USC
AD6426
Buffered UART Mode (Booting/Data Services) This mode attaches the H8/DSP buffered UART to the USC, bringing out either the serial bit rate clock or the Modem Control Signal RI. This is the default mode when the phone is powered up. The BOOTCODE pin will be latched on RESET high. If BOOTCODE is high at RESET, execution begins from the Boot ROM which will configure the buffered UART to download the FLASH programming code into RAM. The FLASH program itself is also downloaded via the UART. An external Data Terminal Adapter can also be used. In this case Data Services are done external to the phone and then transferred to and from the H8. With the external Data Terminal Adapter, the serial bit rate clock output is selected for USCRI pin. This mode can be used for a variety of H8 debug tasks as the UART can be used to simply shift debug information out. Note that when in this mode if the handshake signals and serial bit clock are not required, the RTS and RI pins can be used as extra GPO, and the CTS pin used as an extra GPI. Time-shared Mode (Multi-switch) This mode allows time multiplexed communication with both the H8 and DSP. This is most useful as a hands-free solution, but can be used for other purposes also e.g., DAI Transcoding Testing. This mode is used for DAI testing of the DSP's speech transcoder in which the DSP's SPORT0 is connected to the USC through the Multi-switch. DAI Acoustic Mode Testing This mode is used for DAI testing of the 6425's phone's acoustic properties. The VSPORT of the 6425 connects to the USC through the Multi-switch. IQ Monitoring This mode is used for testing the RF receive path and allows access to the I and Q samples from the AD6425. The AD6425 signals are simply routed to the USC. This means that the clock and frame sync are provided by the 6425 as well. 16 bit Mode This mode connects the synchronous data path to the SDIR/SDOR H8 Peripheral Control Registers, giving the H8 full access to the synchronous port bandwidth. This allows a fast synchronous communication to an external device, and is intended to be used for a fast download mechanism.
* * * * * * * * *
Flash code download for manufacturing and updates Booting - UART interface used to download programs to H8 memory DAI Acoustic mode testing - connects System Simulator (SS) directly to EVBC DAI Transcoding mode - connects SS to 6426 for speech codec testing External DTA (Data Terminal Adapter) - asynchronous link for MSDI interface RS232 port - for on-board data services H8 debug / monitor Hands-free operation - time shared VBC and H8 port Receive I/Q monitoring
The Universal System Connector (USC) of the 6426 is designed such that no external glue logic is required to achieve this multi-purpose functionality. Furthermore, since the USC's function is related to the voiceband and I/Q data serial ports, the USC block is also responsible for the correct configuration of these serial data streams. The actual system connector has the minimum number of pins to achieve the needed functionality. This save system pins, and allows for a more reliable connector from a manufacturing and mechanical standpoint. The USC defines a 5 pin connector that multiplexes asynchronous, synchronous, and modem control signals as needed: Name USCRX USCTX USCRTS USCCTS USCRI I/O I O O I/O 1/O Function Receive Data Transmit Data Ready to Send Clear to Send / Transmit Frame Sync Ring Indicator / Serial Clock
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Keypad / Backlight / Display Interface This interface combines all functions of display and keyboard as shown in Table 10. Table 10. Keypad / Backlight / Display Interface Name KEYPADROW5 : 0 KEYPADCOL3 : 0 BACKLIGHT DISPLAYCS LCDCTL GPIO3 GPIO4 I/O I O O O O O O Function Keypad row inputs Keypad column strobes Backlight control Display Controller chip select LCD Control / Serial Display Data Output Serial Display Data Output Serial Display Clock Output Bit 1 0 0 1 1 Bit 0 0 1 0 1 Frequency 6.3475 kHz 12.695 kHz 25.390 kHz 50.780 kHz
AD6426
Bit 2 1: 0 BACKLIGHT CC Control Register 50 Modulate 1 Backlight LED Control (1:0)
The frequency is determined by the flags Backlight LED Control (1:0) in the same register as shown in Table 11. Table 11. Backlight Frequency
By providing 4 keypad-column outputs (open drain, pull low) and 6 keypad-row inputs the AD6426 can monitor up to 24 keys. Additionally, an extra column can be implemented by using the "ghost column" method for a total of 30 keys. The H8 processor is interrupted whenever a key is pressed. The KEYPADCOL pins are connected to the Keypad Column3-0 flags in the KEYPAD COLUMN CC Control Register 9. Bit 3:0 KEYPAD COLUMN CC Control Register 9 Keypad Column 3-0
Duty cycle can be selected between 0 and 124/128 in 32 steps of 4/128 by programming the Backlight Duty Cycle (4:0) flags in the POWER CONTROL INTERNAL CC Control Register 44. Bit 7:3 POWER CONTROL INTERNAL CC Control Register 44 Backlight Duty Cycle (4:0)
The active period is determined according to the formula: Active (high) Period = Backlight Duty Cycle (4:0) x 4 128
The six KEYPADROW pins are connected to the Keypad Row 5-0 flags in the KEYPADROW CC Control Register 10. Bit 5:0 KEYPADROW CC Control Register 10 Keypad Row 5-0
The 6426 offers both parallel and serial interfaces for connecting to LCD display controllers. The parallel interface to a LCD controller is provided by two dedicated control signals (LCDCTL and DISPLAYCS) and parts of the address and data bus. A typical interface is shown in Figure 5.
LCD Controller
DATA (7:0) R/W E RS CS
One backlight control output (BACKLIGHT) is provided, which can be modulated to provide the same perceived brightness for a reduced average current. Switching frequency as well as duty cycle can be modified to compensate for ambient lighting levels and changing battery voltage. The BACKLIGHT output is activated by setting the Backlight1 flag in the SYSTEM CC Control Register 0. Bit 5 SYSTEM CC Control Register 0
AD6426
DATA (15:8) HWR LCDCTL ADD(0) DISPLAYCS
Backlight 1 Once activated, an internal PWM circuit can control the frequency and the duty cycle of the output signal. The PWM circuit is enabled by the Modulate1 flag in the BACKLIGHT CC Control Register 50. To switch the backlight continuously on, enable the Backlight 1 flag and disable the Modulate 1 flag.
Figure 5. Parallel Display Interface The on-chip control circuit automatically generates wait states for interfacing to external display devices.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Serial Display Interface The serial display interface is compatible with display drivers by Motorola and Seiko-Epson. The display driver by Motorola uses an SPI serial bus which requires an inverted or delayed clock in comparison to the Seiko-Epson type display driver. In the Motorola mode the data is delayed by one half clock cycle such that the data is driven on the rising edge of SCLK instead of on the falling edge. The serial display interface consists of four pins; a serial data output (DISPD0), clock (DISPCLK), chip enable (DISPEN) and address (DISPA0). These pins are multiplexed with GPIO4, GPIO3, LCDCTL and DISPLAYCS. Bit 1 (DISP) of the MEMIF H8 Peripheral Control Register 80 controls the configuration of the display interface. With this set to 0, the parallel display interface is used. Setting this bit to one enables the use of the serial display interface. This bit is set to 0 on reset. Bit 4 (SERDISP MODE) of the SERDISPLAY/NMI H8 Peripheral Control Register 106 controls the serial display mode. The default setting is Seiko-Epson mode. To enable the Motorola mode the user must set the register bit to ONE. Display Reset No dedicated pin is used to reset the display sub system. It is recommended that the VBCRESET pin is used for this function by connecting the Reset input on the display and the Reset input on the VBC to the AD6426 VBCRESET pin. The VBC and display cannot be reset independently. However one of the GPIO pins can be used to reset the display separately. Battery ID Interface The AD6426 provides a single-wire interface compatible with the Dallas SemiconductorTM DS2434or DS2435 Battery Identification chip. The communication protocol supports three operations: RESET, READ and WRITE. These operations permit reading the present status off the battery and writing updated information to the ID chip. The interface is available as the BATID function multiplexed on the GPIO5 pin.
AD6426
Bit 3 (DALLAS EN) of the MEMIF H8 Peripheral Control Register 80 controls the enabling of the battery ID interface module. Setting this bit to zero enables the interface, resetting the bit disables it. This bit is set to one on reset. EVBC Interface The AD6426 interfaces directly to the Enhanced Voiceband Baseband Converter AD6425 through the pins shown in Table 12.The communication is performed through three serial ports: the Auxiliary Serial Port (ASPORT), the Baseband Serial Port (BSPORT) and the Voiceband Serial Port (VSPORT). Layer 1 software enables/disables the clock output in order to reduce system power consumption to a minimum if operation of the AD6425 is not required. Figure 6 shows the interface between the AD6426 and the AD6425 as well as to the AD6432 IF chip. Table 12. EVBC Interface Name CLKOUT EVBCRESET ASPORT ASDO ASOFS ASCLK ASDI BSPORT BSDO BSOFS BSCLK BSIFS BSDI VSPORT VSDO VSDI VSCLK VSFS I/O O O O O O I O O I I I O I I I Function Clock Output to EVBC Reset Output to EVBC Data Output Output Framing Signal Clock Output Data Input Data Output Output Framing Signal Clock Input Input Framing Signal Data Input Data Output Data Input Clock Input Input/Output Framing Signal
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
CLKIN MCLK RESET ASDI ASDIFS ASDOFS ASCLK ASDO BSDI BSDIFS BSCLK BSDO BSDOFS MODE VSDO VSDI VSCLK VSFS VSDI VSDO VSCLK VSFS
AD6426
13 MHz XTAL
CLKOUT VBCRESET ASDO ASOFS ASCLK ASDI BSDO BSOFS BSCLK BSDI BSIFS
AD6425
AFC
XTAL TCOR BREFOUT GREF
RFCLK
AD6432
MXOP IFHI FILTER
AGC ITXP ITXN QTXP QTXN IRXP IRXN QRXP QRXN
GAIN ITXP ITXN QTXP QTXN IRXP IRXN QRXN QRXP OSEN RXPU TXPU RFHI RFLO
FILTER
RMX_OUT MODP MODM TX_IN
FREF
TMX_OUT
PAs & Control
TX
FILTERS
LNA-IN
RXON TXON RAMP
DUALBAND RF FRONT-END
RXON TXON GSM_ON DCS_ON
RX
RXON TXENABLE GPIO2 GPIO1 RADIOPWRCTL
BANDSELECT0 BANDSELECT1
RFLO
GSM_ON RFLO DCS_ON SYNTHCLK SYNTHDATA SYNTHEN0 GPIO7 TXPHASE TXPA DCLK DATA ENB RFCLK
VCOs + SYNTHESIZERS
ANTENNASELECT
Figure 6. EVBC and Radio Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Radio Interface
The AD6426 Radio Interface has been designed to support direct connection to the ADI IF-Chips AD6432, while providing full backwards compatibility to existing radio designs interfacing to the AD20msp410 and AD20msp415. Additionally the AD6426 Radio Interface supports radio architectures based on Siemens, TTP/Hitachi or Philips RF chipsets. The Radio Interface of the AD6426 consists of 16 dedicated output pins listed in Table 13. Together with two optional general purpose I/O-pins they provide a flexible interface to a variety of radio architectures for both 900 MHz and 1800/1900 MHz operation.
AD6426
CONTROL), gated with RADIO POWER CONTROL to force a low output when the Radio is off. In order to increase the flexibility of the AD6426, three pins in the Radio Interface are multiplexed with GPO functions. The pins multiplexed are: SYTHEN1, AGCA and AGCB, with the default function being the Radio Interface. The mode of these pins is controlled by the new ccGPO Channel Codec Register: The GPO[n]Sel bit selects the function of the pin. Setting GPO[n]Sel to one will enable the pin to be controlled by the GPO[n] bit. The GPO[n]Sel bit will override any other pin function selection. Generic Pins The following three pins have the same functionality in all types of radio architectures: RADIOPWRCTL This output signal is typically used to power down the oscillators and prescalers during Idle mode and is directly controlled by the Radio Power Control flag in the POWER CONTROL EXTERNAL CC Control Register 45. Bit 1 POWER CONTROL EXTERNAL CC Control Register 45 Radio Power Control Table 13. Radio Interface Name GPIO1 GPIO2 RADIOPWRCTL GPIO6 GPIO7 TXPHASE TXENABLE TXPA RXON CALIBRATERADIO SYNTHEN0 SYNTHEN1 SYNTHDATA SYNTHCLK AGCA AGCB I/O O O O O O O O O O O O O O O O O Function BANDSELECT1 BANDSELECT0 Radio Powerdown Control VBIAS ANTENNASELECT Switches PLLs (Rx / Tx) Transmit Enable Power Amplifier Enable Receiver on Radio Calibration Synthesizer 0 Enable Synthesizer 1 Enable Synthesizer Port Serial Data Synthesizer Port Clock AGC Control A AGC Control B
Dual Band Control
To support dual band handsets BANDSELECT[1:0] signals are provided. BANDSELECT0 is multiplexed with GPIO[2], with the default function of this being GPIO[2]. BANDSELECT1 is multiplexed with GPIO[1], the default function being GPIO[1]. For Dual Band solutions requiring a single band select bit, the BANDSELECT0 function is enabled by asserting the BAND EN bit. In order to set BANDSELECT0 high/low and cause the radio module to operate in the appropriate band, the least significant bit (bit 0) of the relevant 32 bit register for Dynamic Synthesizer 1 must be written, i.e. different values may be set for Rx, Tx and Monitor but only for Dynamic Synthesizer 1. BANDSELECT0 is sampled internally and is valid from the beginning of data serialization, both for on demand (immediate) loading and ordinary interrupt driven loading. The BANDSELECT0 signal will remain in this known state until the next time there is any serialization of data for Dynamic Synthesizer 1, when a new sample will be taken of the least significant bit of the 32 bit synthesizer register currently being serialized. Full control is provided over the number of bits to be shifted out to the synthesizer and so it is intended that this bit count will always be less than 32 when using the BANDSELECT0 feature in order to prevent shifting the control bit out. BANDSELECT0 is gated with RADIO POWER CONTROL to ensure that whenever the RADIO is off, BANDSELECT0 is forced to a low state. For Dual Band Solution requiring two band select bits, one for GSM900, and one for DCS1800, then both BANDSELECT0 and BANDSELECT1 are enabled by asserting both the BAND EN and DCSSEL EN bits. The BANDSELECT0 output is driven as in the single enable mode (described above), and the BANDSELECT1 output is the inverted output of the raw BANDSELECT0 output (prior to gating with RADIO POWER
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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GPIO6 - VBIAS This general purpose I/O pin can be used to control the powering up/down of a separate voltage converter, which may be needed to provide the supply voltage for GaAs RF Power Amplifiers. Significant turn-on time of the voltage converter requires an early power-up signal, which is provided by GPIO6. This control is achieved entirely through a software driver, without hardware support. Since this function is not needed for all radio solutions, the GPIO pin can be used for other functions if not required. GPIO7 - ANTENNASELECT This general purpose I/O pin can be used to switch between two different antennas, as required, when the mobile radio is used in conjunction with a car-kit with external antenna. This control is achieved entirely through a software driver, without hardware support. Since this function is not needed for all radio solutions, the GPIO pin can be used for other functions if not required. Tx Timing Control The following 5 radio interface pins serve different functions depending on the radio architecture: TXPHASE The purpose of this signal is to switch PLLs between Rx and Tx modes. The signal is generated under control of the flags TXPHASE Enable and TXPHASE Polarity of the RADIO CONTROL CC Control Register 2. Bit 6 RADIO CONTROL CC Control Register 2 TXPHASE Polarity Controls the polarity of the output TXPHASE. When set to 1, TXPHASE is active low; When set to 0, TXPHASE is active high. TXPHASE Enable Enables the output pin TXPHASE if set to 1. Transmit Enable Enables the output pin TXENABLE if set to 1.
AD6426
TXPA This signal is used as a power amplifier (PA) enable and/or as a control signal for the PA control loop. This allows the PA to be isolated from the supply outside the Tx-slot to save current. In the PA control loop it can be used to control the dynamics of the loop. The flag Tx Pa Polarity in the TRAFFIC MODE CC Control Register 6, provides independent control for the TXPA signal. Bit 7 TRAFFIC MODE CC Control Register 6 Tx Pa Polarity; active high, when reset
TXPA is derived from the leading edge of TXENABLE signal shown in Figure 7.
TXENABLE TD TXPA TW
Figure 7. Timing of TXPA The parameter TD is a programmable delay (0 to 1023 QBIT) to accommodate the EVBC settling time. TD is therefore a 10 bit value, accessed via the TXPA OFFSET 1 CC Control Register 73 and the TXPA OFFSET 2 CC Control Register 74. Bit 1:0 Bit 7:0 TXPA OFFSET 1 CC Control Register 73 TD (9:8) TXPA OFFSET 2 CC Control Register 74 TD (7:0)
3 0
The parameter TW is a programmable width (0 to 1023 QBIT) which defines the PA enable time. TW is therefore a 10 bit value, accessed via the TXPA WIDTH 1 CC Control Register 75 and the TXPA WIDTH 2 CC Control Register 76. Bit 1:0 Bit 7:0 TXPA WIDTH 1 CC Control Register 75 TW (9:8) TXPA WIDTH 2 CC Control Register 76 TW (7:0)
In radios based on the TTP/Hitachi solution, this signal can be used to switch the VCOs. In radios based on the Siemens or Philips solution, this signal can be used for control switching PLLs, or band switching UHF PLLs. TXENABLE This signal enables the RF modulator and transmit chain including the PA, and controls the TXON-pin of the AD6425. The signal is generated under control of flag Transmit Enable of the RADIO CONTROL CC Control Register 2.
If TW is set to zero, then TXPA will be disabled.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Rx Timing Control RXON The signal at the output pin RXON is generated by the function Receive Enable OR Monitor Enable of the RADIO CONTROL CC Control Register 2. It can be used to enable the RF receiver and controls the RXON-pin of the AD6425. In radios based on the Siemens solution this signal would be connected to the RXON1 input. Additional RXON derived signals are provided to support this solution. Bit 2 1 RADIO CONTROL CC Control Register 2 Monitor Enable Receive Enable 6
AD6426
Synthesizer Control The radio interface of the AD6426 supports 2 dynamic synthesizers, with each capable of downloading data on demand. The two Synthesizer Load Dynamic flags located in the SYNTH CONTROL CC Control Register 38, will set the synthesizer interface to load 3 consecutive long-words from Layer 1. Bit 7 SYNTH CONTROL CC Control Register 38 Synthesizer Enable Polarity Selects the polarity of the SYNTHEN outputs. If set to 0, SYNTHEN is an active low signal, if set to 1, SYNTHEN is an active high signal. Synthesizer Enable Type Selects the active period of the SYNTHEN outputs. When set to 0, SYTHEN is active for all data values determined by SYNTHESIZER BIT COUNT; when set to 1, SYNTHEN goes active after the last bit for one SYNTHCLK period. Synthesizer Load Dynamic 1 (SLD1) Synthesizer Load Dynamic 0 (SLD0)
CALIBRATERADIO The 4 modes of the Autocalibrate signal (Type 0 & 1, AutoCal on/off) are provided as required by the ADI or Philips solution and shown in Figure 8.
RXON RxEnable RxEnable Start (early) Start (late) AutoCalibrateEnd TYPE=0, AUTOCAL=0 RxEnableEnd
2 1
TYPE=0, AUTOCAL=1
When using the Configure Dynamic Synthesizer flag in the SYNTH BIT COUNT CC Control Register 37, the downloadon-demand function is applied to the synthesizer selected by SLD0 or SLD1. Bit Figure 8. Autocalibration 6 SYNTH BIT COUNT CC Control Register 37, Configure Dynamic Synthesizer
TYPE=1, AUTOCAL=0
TYPE=1, AUTOCAL=1
The flags Autocalibrate and Calibrate Radio in the SYSTEM CC Control Register 0 are ORed and connected to the output pin CALIBRATERADIO. Bit 7 3 the SYSTEM CC Control Register 0 Autocalibrate Enables the autocalibrate function if set to 1; Calibrate Radio
Each dynamic synthesizer is comprised of three 32-bit word registers, for the Rx, Tx and Monitor phases. The download on demand uses the Rx register only for the respective synthesizer. Bit 7:0 Bit SYNTHESIZER 1 CC Control Register 40 Synthesizer (31:24) SYNTHESIZER 2 CC Control Register 41 Synthesizer (23:16) SYNTHESIZER 3 CC Control Register 42 Synthesizer (15:8) SYNTHESIZER 4 CC Control Register 43 Synthesizer (7:0)
The type of autocalibration is set in the TRAFFIC MODE CC Control Register 6 Bit 3 TRAFFIC MODE CC Control Register 6 Autocalibration Type
7:0 Bit 7:0 Bit 7:0
In radios based on the Siemens chipset, this signal would connect to the RXON2 input. The required behavior is enabled by selecting the Type 1 CalibrateRadio function.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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The two dynamic synthesizers are programmable as follows, while each synthesizer may be independently disabled, through the two Disable Synthesizer flags in the SYNTHESIZER PROGRAM CC Control Register 72. Bit 5 4 3 2 1:0 SYNTHESIZER PROGRAM CC Control Register 72 Disable Synthesizer 1 Disable Synthesizer 0 Synthesizer Enable Select Synthesizer Mode Pin Mode (1:0) 0
AD6426
Bit 5 SYNTH CONTROL CC Control Register 38 Synthesizer Clock Polarity Selects the edge, on which synthesizer data and enable will be clocked out. Negative edge, when set to 0; positive edge, when set to 1. Synthesizer Clock; selects the frequency of SYNTHCLK output. SYNTHCLK = 1.625 MHz if set to 0 (default), SYNTHCLK = 6.5 MHz if set to 1.
SYNTHEN0 : 1 The AD6426 provides enable signals for two independent synthesizers. These signals are available at the output pins SYNTHEN0 and SYNTHEN1. The polarities of these signals are individually programmable; i.e. bit 7 of CC Control Register 38 is applied to the synthesizer selected by either bit 2 or bit 1 of the same register. SYNTHDATA and SYNTHCLK Three Modes can be selected to support different radio architectures. The selection of the Pin-Mode is done by the two Pin Mode flags in the SYNTHESIZER PROGRAM CC Control Register 72 as shown in Table 14. Table 14. Pin Mode Bit 1 0 0 1 1 Bit 0 0 1 0 1 Mode Mode 1 (default) Mode 1 Mode 2 Mode 3
In Modes 2 and 3, the outputs of these two pins are multiplexed with flags of the internal DSP as indicated in Table 16. The function of DSPFLAG1 o Synthesizer Data is defined as: The output is that of DSPFLAG1 except when the synthesizer interface is active. In this case the synthesizer output has priority. The same applies to DSPFLAG2 o Synthesizer Clock. Table 16. Pin Function in Modes 2 and 3 AD6426 Pin SYNTHDATA SYNTHCLK Function DSPFLAG1 o Synthesizer Data DSPFLAG2 o Synthesizer Clock
AGC Control AGC programming is achieved in one of three ways: The first is a gain select approach, whereby the DSPFLAG0 and DSPFLAG1 are used as a 2-bit gain selector (AGCA, AGCB). This is available in Mode 1 and the flags are under direct control of the internal DSP and are timing independent of the synthesizer interface. Table 17. Pin Function in Mode 1 AD6426 Pin AGCA AGCB Function DSPFLAG0 DSPFLAG1
The default is Mode 1, which supports TTP/Hitachi Bright and Philips radio architectures. Mode 2 also supports a Philips architecture, while Mode 3 supports a Siemens architecture. In Mode 1, the pins SYNTHDATA and SYNTHCLK have their original functionality; i.e. SYNTHDATA is the data output and SYNTHCLK is the clock output of the serial synthesizer interface. Clock polarity and frequency are programmed in the SYNTH CONTROL CC Control Register 38. Table 15. Pin Function in Mode 1 AD6426 Pin SYNTHDATA SYNTHCLK Function Synthesizer Data Synthesizer Clock
The second is through the DSP combined with the serial synthesizer interface, as defined in Mode 2. The function of DSPFLAG0 o SYNTHEN1 is defined as: The output is that of DSPFLAG0 except when the synthesizer interface is active. To support the Philips chipset whereby the AGC and the PLL are programmed over the same enable line, the AGCA pin is multiplexed to provide a SYNTHEN1 gated with DSPFLAG0. This pin would be wired instead of the SYNTHEN1 pin. Since the DSP would program the AGC during RXON, and the synthesizers are reprogrammed following the end of the active phase, no conflict can occur.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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In Modes 2 and 3, PLL programming occurs on any of Rx, Tx and MonEnableEnd through the synthesizer interface. Additionally, AGC programming, controlled via the DSP, is performed during RXON. Table 18. Pin Function in Mode 2 AD6426 Pin AGCA AGCB Function DSPFLAG0 o SYNTHEN1 DSPFLAG1
AD6426
The third mode is for support of the Siemens chipset, providing an independent AGC enable from SYNTHEN using the DSP Flag 0. The same serial interface constraints from Mode 2 apply. Additionally, the output OCE is provided. This is the Offset Correction Enable, derived from the RxEnableStartEarly and RxEnableStartLate timing signals as shown in Figure 9. Table 19. Pin Function in Mode 3 AD6426 Pin AGCA AGCB Function DSPFLAG0 OCE
RxEnableStartEarly RxEnableStartLate RXON
OCE
Figure 9. OCE Signal
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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TEST INTERFACE The AD6426 provides a complete JTAG test interface. The functionality of these pins are shown in Table 20. Furthermore, these pins can assume a different functionality described in detail in the chapter MODES OF OPERATION. Table 20. Test Interface Name JTAGEN TCK TMS TDI TDO I/O I I I I O Function JTAG enable (internal pull down resistor) JTAG test clock input JTAG test mode select JTAG test data input JTAG test data output 0111 10001110 1111 Bypass Bypass Table 21. JTAG Instructions Instr. Register 4321 0000 0001 0010 0011 01000101 0110 Mode D ExTest Clamp Sample/PreLoad DoBist Code Comments
AD6426
Public Instruction Optional Public Instruction Public Instruction Private Instruction Engineering Mode Test Reserved Private Instruction H8 Emulation Reserved Public Instruction Selects Mode A Public Instruction Selects Mode A (default)
JTAG Port The AD6426 provides full IEEE 1149.1 compliance. The JTAG Port must be run at a frequency of 5 MHz or less. The JTAG Port is explicitly enabled through JTAGEN. When disabled, the corresponding pins are re-used for the AD6426 Feature Modes. The JTAG interface implements four registers shown in Figure 10. The content of the Instruction register selects one of these four registers.
Boundary Register 161 162 Bypass Register 163 1 1 3 2
ExTest Instruction The ExTest instruction is used to force input or output conditions on the boundary scan cell. Clamp Instruction This optional public instruction is similar to the Bypass instruction, except that once loaded, it will force the values held in the boundary scan chain onto the corresponding outputs of the device. This enables all output and bidirectional pads to be fixed, allowing other parts on the PCboard to be tested without interference from the AD6426, while at the same time selecting the Bypass register for the shortest possible scan path. All input activity to the AD6426 will be ignored during this time, since all inputs are driven from the preloaded values in the boundary scan chain. Typically therefore this instruction would be preceded by the Sample/Preload instruction. This instruction is only valid during the normal operation of the AD6426; i.e. in Mode A. Sample/Preload Instruction The Sample/Preload instruction is fully IEEE compliant. Boundary Register The boundary cell structure is based on the I/O definition in Mode A, and hence pins which are outputs only in this mode, but become inputs in another mode, do not support input scan cells, and vice versa. Table 22 shows the complete Boundary register.
TDI 8 4 7 6
Bist Register 5 4 3 2 1
TDO
1 Instruction Register 3 2
Figure 10. JTAG Registers The instruction register contains 4 bits, and supports the instructions listed in Table 21. Instruction register values 01XX all select the bypass register when JTAG compliance is enabled. Values 00XX control the AD6426 I/O as defined in Mode A, and therefore should not be used in any other mode.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Table 22. Boundary Scan Path
TDO # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Cell Name SIMCARD SIMCARD SIMCARD SIMCLK SIMDATAOPEN SIMDATAOP SIMDATAIP SIMRESET SIMPROG SIMPROG SIMPROG SIMSUPPLY GPIO0EN GPIO0 GPIO0 GPIO1EN GPIO1 GPIO1 WR FLASHPWD FLASHPWD FLASHPWD DATA0 : 7EN DATA0 DATA0 DATA1 DATA1 DATA2 DATA2 DATA3 DATA3 DATA4 DATA4 DATA5 DATA5 DATA6 DATA6 DATA7 DATA7 LBS UBS RD DATA8 : 15 EN B O I O T O I O B O I O B O I B O I O B O I B O I O I O I O I O I O I O I O I O O O B # 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Cell Name DATA8 DATA8 DATA9 DATA9 DATA10 DATA10 DATA11 DATA11 DATA12 DATA12 DATA13 DATA13 DATA14 DATA14 DATA15 DATA15 ROMCS RAMCS ADD0 ADD1 ADD2 ADD 3 ADD4 ADD5 ADD6 ADD7 ADD8 BOOTCODEEN ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 USCRTS USCCTSEN USCCTS O I O I O I O I O I O I O I O I O O O O O O O O O O O I O O O O O O O O O O O O I B O # 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Cell Name USCCTS USCTX USCRXEN USCRX USCRX USCRI GPIO9EN GPIO9 GPIO9 GPIO8EN GPIO8 GPIO8 IRQ6 RESET KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 KEYPADCOL0EN KEYPADCOL0 KEYPADCOL1EN KEYPADCOL1 KEYPADCOL2EN KEYPADCOL2 KEYPADCOL3EN KEYPADCOL3 GPCS OSC13MON BACKLIGHT DISPLAYCS LCDCTL GPIO3EN GPIO3 GPIO3 GPIO4EN GPIO4 GPIO4 GPIO5EN GPIO5 GPIO5 GPIO6EN I O B O I I B O I B O I I I I I I I I I T O T O T O T O O O O O O B O I B O I B O I B #
AD6426
Cell Name O I B O I I O O O O O O O O O O O I B O I O O O I O I I I O O O O O I I I T O B O I O O
130 GPIO6 131 GPIO6 132 GPIO7EN 133 GPIO7 134 GPIO7 135 CLKIN 136 TXENABLE 137 RADIOPWRCTL 138 CALIBRATERADIO 139 TXPA 140 AGCB 141 AGCA 142 SYNTHCLK 143 SYNTHDATA 144 SYNTHEN0 145 SYNTHEN1 146 PWRON 147 OSCIN 148 GPIO2EN 149 GPIO2 150 GPIO2 151 TXPHASE 152 ASDO 153 ASOFS 154 ASDI 155 ASCLK 156 BSCLK 157 BSDI 158 BSIFS 159 BSOFS 160 BSDO 161 CLKOUT 162 RXON 163 VBCRESET 164 VSCLK 165 VSDI 166 VSFS 167 VSDOEN 168 VSDO 169 EEPROMDATAEN 170 EEPROMDATA 171 EEPROMDATA 172 EEPROMCLK 173 EEPROMEN TDI
Notes: The boundary scan supports only pin functionality and signal directions of Normal Mode (A); see chapter "Modes of Operation". Cells can be input (I) or output cells (O) which correspond to the pins with the same name, or internal control cells shown in ITALIC. Control cells are either bi-directional control cells (B), or tri-state output control cells (T). When type-B cells are loaded with 0, the referred pins become driving output pins, otherwise the pins are inputs. When type-T cells are loaded with 1, the referred pin will be tri-stated, otherwise the pin is an output.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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DoBist Instruction This instruction is provided to support engineering mode test. When the instruction is loaded, it will generate an NMI to the H8 processor. This will enable special software to be executed which can be used to test the operation of the device. During this time, the 8-bit DoBist register is selected for scan, enabling a result code for the test to be scanned out. For the duration of the test, all I/O retain their normal function. The test program must therefore cope with undefined inputs, but is able to communicate with other devices to extend the test procedure. This allows the NMI to be generated during normal phone operation. This instruction is only valid during the normal operation of the AD6426; i.e. in Mode A. Mode D Instruction This instruction switches the AD6426 into the H8 Emulation Mode (Mode D). It is only valid to switch modes while the AD6426 is held in reset. Reset To comply with the IEEE specification, the JTAG interface will be forced to reset whenever the JTAG Port is re-enabled. This will select the Bypass register and force the AD6426 into the Normal Mode (Mode A). Debug Port Interface In normal (voice-service) operation, the Universal Serial Port can be used as a monitor port, which allows monitoring internal operation of the channel codec section. However, during the use of GSM Data Services, the USC is engaged in data communication and cannot be used for monitoring. The 6426 provides a Debug Port to enable monitoring and debugging in this case. This is in the form of a simple 2 pin UART. The communication format is fixed at 9600 baud, 8 data bits, one stop bit, no parity, asynchronous communication. Operation of the Debug Port is under control of the Layer 1 software. Two of the GPIO pins can be programmed to be used as the Debug Port: Pin Name GPIO8 GPIO9 New Function TXDATA RXDATA
AD6426
Table 23. Modes of Operation Mode of Operation A B C D Normal Mode Reserved Reserved Emulation Mode (H8)
Normal Mode (Mode A) This mode is used during normal operation of the AD6426. All JTAG-pins have their normal functionality, when enabled by JTAGEN and can be used for production test. Emulation Mode (Mode D) Selecting Mode D allows the emulation of the internal H8 processor. In this Mode several pins assume a new functionality or are no longer available. Table 24 lists all pins, which have different functionality or direction in the Emulation Mode compared to the Normal Mode. In Emulation Mode the internal DSP remains active but will not have access to external memory devices. The internal H8 will be switched into hardware stand-by mode; the LCD controller interface and Boot Code ROM remain functional. CCIRQ0 : 2 are channel codec interrupts to the emulator. CCIRQ2 is defined in CC Control Registers 77 and 78. Table 24. Pin Functions in Mode D Pin Name in Normal Mode (A) IRQ6 ADD19 : 16 ADD15 : 0 DATA7 : 0 RD HWR LWR RAMCS SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY GPIO9 GPIO8 Pin Function in Emulation Mode (D) CCCS ADD15 : 0 RD HWR CCIRQ0 CCIRQ2 CCIRQ1 H8CS0 CCGPIO8 I TRI I TRI I I TRI TRI TRI TRI - O I O O O O I I/O TRI
The serial port can be enabled by asserting the flag DATA SERIAL PORT SELECT in CC Control Register 7. MODES OF OPERATION The AD6426 can be switched between two main operating modes, using instructions downloaded via the JTAG interface. This must be done while the AD6426 is held in reset. Once the instruction load is completed the pins are immediately set to reflect the new operating mode. Table 23 shows these modes. The modes B and C are reserved and are not available to the user.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Pin Name in Normal Mode (A) GPO10 GPCS FLASHPWD DISPLAYCS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Pin Function in Emulation Mode (D) WAIT Forced High DISPLAYCS Reserved Forced High/ BANDSELECT1 Forced High/ BANDSELECT0 Forced High/DISPA0 Forced High/DISPCLK Forced High/BATID Reserved Reserved O TRI O I/O O O O AD6426 Pin O O O O TRI TCK TMS TDO TDI EEPROMCLK FLASHPWD can also be used as WAIT input, in which case it is routed through and gated with the LCDWAIT to be output on the WAIT output pin GPO10/ADD20. If the on-chip LCD controller is not used in emulation, then ADD20 pin can be used as ccGPO(10). FEATURE MODES Two additional features can be enabled under software control. These are; DAI Mode (Digital Audio Interface) and HSL Mode (High Speed Logging) used to monitor the operation of the on-chip DSP. DAI Mode This mode is selected during type approval, when Digital Audio Interface is required. To enable this feature, the JTAGEN pin must be de-asserted, upon which the JTAG pins TMS, TDI and TDO are re-assigned as shown in Table 25. The default feature mode thus enabled is DAI. In addition, the voiceband serial port signals are made available through the USC to facilitate testing of the speech transcoder as well as the phone's acoustic properties. The DAI box interface product is available upon request from Analog Devices. Table 25. DAI Mode AD6426 Pin VSCLK VSFS VSDO VSDI TMS TDI TDO Function in DAI Mode MSCLK MSFS MSRXD MSTXD DAIRESET DAI1 DAI0 I/O I I O I O O I EERPROMEN
AD6426
High Speed Logging This mode is selected for monitoring the operation of the internal DSP during the development and field test phase. When the JTAGEN pin is de-asserted and the HSLEnable flag in the TESTADDRESS CC Control Register 33 is set, a high speed logging port is mapped on the JTAG- and EEPROM pins as shown in Table 26. The internal DSP must then be instructed via Layer 1 to output logging messages onto the HSL pins. Table 26. HSL Mode Function in HSL Mode HSLDO0 HSLDO1 HSLDO2 HSLDO3 HSLCLK HSLFS O O O O O O
The High Speed Logging port (HSL) is an unidirectional port which supplies nibble-wide synchronous data from the internal DSP to an external data logger. The data logger will be connected to a PC which will be responsible for presenting the data to the user. The PC is able to configure the HSL via either one of the serial interfaces. The HSL is enabled as follows: * * * The JTAGEN pin is set to 0 The H8 enables the HSL logic by setting the HSLEnable flag On a command issued through the Data Interface, the H8 configures the DSP software to enable HSL
The HSLEnable flag is used to deselect DAIRESET in favor of the HSL onto the JTAG pins, and enable the HSL onto EEPROMCLK and EEPROMEN. The DSP sends data over the port by writing to address 0x000 in the Data Memory map. The writes are full 16-bit writes, and can occur at a maximum rate of one write per five 39 MHz clock cycles. Five cycles allow time for the HSL circuit to serialize the 16 bits of data onto the 4-bit data bus with one cycle to spare. HSLFS is used to frame the valid data nibbles. Note that HSCLK is free-running , and that HSLFS and HSLDO3-0 are synchronized to the rising edge of HSCLK.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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The mapping of the DSP data bits to the HSL port bits is: Table 27. Mapping of HSL Port Nibbles DSP Data Bits 23 : 20 19 : 16 15 : 12 11 : 8 HSLDO Nibble 1 2 3 4
AD6426
HSCLK
HSLFS HSLDO (3:0) 1 2 3 4 1
Figure 11. HSL Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
General
Min
-25 2.4 TBD TBD 13 0.250 19.5
SPECIFICATIONS
Parameter
TA , Ambient Operating Temperature VDD , Supply Voltage IDD , Supply Current (Idle Mode) IDD , Supply Current (Talk Mode) fCLKIN , Clock Input Frequency VCLKIN , Clock Input Voltage RCLKIN, Clock Input Resistance (see Note) Logic Inputs VIH , Input High Voltage VIL , Input Low Voltage IIH , IIL Input Current CIN , Input Capacitance Logic Outputs VOH , Output High Voltage VOL , Output Low Voltage IOZL , Low Level Output 3-State Leakage Current IOZH , High Level Output 3-State Leakage Current -10 -10 VDD - 0.4 0.4 10 10 A A -10 TBD VDD - 0.8 0.8 10 Volt Volt A pF
Typ
Max
+85 3.3
Units
C Volt mA mA MHz VPP k
Comments
@ VDD = 3.0 V @ VDD = 3.0 V sine wave, ac-coupled sine wave, ac-coupled
Note: The input impedance of the clock buffer is a function of the voltage and waveform of the clock input signal. For sinusoidal input signals the typical input impedance can be calculated by: RIN [k] = VCLKIN [VPP] x 78
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................. -0.3V to + TBD V Digital I/O Voltage to GND ...................-0.3V to VDD + 0.3V Operating Temperature Range ........................ -25C to +85C LQFP Package Storage Temperature Range .......................... -65C to +150C Maximum Junction Temperature ................................ +150C QJA Thermal Impedance..............................................28C/W Lead temperature, Soldering Vapor Phase (60 sec)........................................... +215C Infrared (15 sec).................................................. +220C PBGA Package Storage Temperature Range .......................... -65C to +150C Maximum Junction Temperature ................................ +150C QJA Thermal Impedance..............................................30C/W Lead temperature, Soldering Vapor Phase (60 sec)........................................... +215C Infrared (15 sec).................................................. +220C
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TA= +25C unless otherwise stated.
ESD SUSCEPTIBILITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may still occur on this device if it is subjected to high energy electrostatic discharges. Therefore, proper precautions are recommended to avoid any performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Clocks
Min Typ 76.9 30 30 76.9 30 30 45 45 45 45 Max Units ns ns ns ns ns ns
TIMING CHARACTERISTICS
Parameter t1 t2 t3 t4 t5 t6 Comment CLKIN Period (see Figure 13) CLKIN Width Low CLKIN Width High CLKOUT Period (see Figure 14) CLKOUT Width Low CLKOUT Width High
100 A
t1
IOL
CLKIN
t3
t2
To Ouput Pin CL 50pF
+2.1V
Figure 13. Clock Input
t4
100 A
IOH
CLKOUT
t6
t5
Figure 12. Load Circuit for Timing Specifications
Figure 14. Clock Output
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Memory Interface
Min Max Units
TIMING SPECIFICATION
Parameter Comment ( Timing for 3-state access, see Figure 15 )
Timing Requirement t10b t12b t17 t19 Control Processor read chip select to data valid Control Processor read address to data valid Control Processor read enable to data valid Control Processor data hold 0
158 162 129
ns ns ns ns
Switching Characteristic t10a t11 t12a t13 t14 t15 t16 t18 Control Processor write chip select setup Control Processor chip select hold Control Processor write address setup Control Processor address hold Control Processor write pulse width Control Processor data setup Control Processor data hold Control Processor read pulse width
WRITE
CS t10a t12a ADD 15:0 t14 HWR/LWR t15 DATA15:0 t16 t13 t11
10 5 10 5 111 68 15 145
ns ns ns ns ns ns ns ns
READ
t10b CS t13 ADD15:0 t12b RD t17 t18 DATA7:0 t19 t11
Figure 15. Memory Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Radio Interface
Min
152 76 60 60 60 -15 50
TIMING CHARACTERISTICS
Parameter
t40 t41 t42a t42b t43a t43b t44
Comment ( see Figure 16 )
Synthesizer clock period Synthesizer clock high Synthesizer data setup Synthesizer data hold Synthesizer enable delay for Type 0 Synthesizer enable delay for Type 1 Synthesizer enable width for Type 1
Max
615 307 85 85 85 10 90
Units
ns ns ns ns ns ns ns
t40 SYNTHCLK t42a SYNTHDATA t43a SYNTHEN[0:1] TYPE 0 0 1 t42b
t41
2
n-2
n-1
n
t41 t40 SYNTHCLK t42a SYNTHDATA 0 1 t42b SYNTHEN[0:1] TYPE 1 t44 2 n-2 n-1 n t43b
Figure 16. Synthesizer Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
High Speed Logging Interface
Min Typ 25.6 8.3 8.3 0 0 15 15 Max Units ns ns ns ns ns
TIMING CHARACTERISTICS
Parameter t50 t51 t52 t53 t54 Comment ( see Figure 17) HSCLK Period HSCLK Width Low HSCLK Width High HSCLK to HSLDO HSCLK to HSLFS
t50 HSCLK t54 HSLFS t53 HSLDO3:0 1
t52 t51
2
3
4
1
Figure 17. High Speed Logging Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Data Interface
Min Typ Max Units ns 100 100 0 ns ns ns
TIMING CHARACTERISTICS
Parameter t60 t61 t62 t63 Data Interface (see Figure 18) Clock Period Transmit Data Delay time Receive Data Setup time Receive Data Hold time
t60 MONCLK
t61
MONTX t62 MONRX t63
Figure 18: Data Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Test Interface
Min Typ Max Units ns 120 120 ns ns
TIMING CHARACTERISTICS
Parameter t64 t65 t66
*
JTAG Port TCK Period
* *
200 80 80
TCK Width Low
TCK Width High*
Note: These parameters have been functionally verified, but not tested.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
EVBC Interface ASPORT
Min Typ 384 20 20 20 20 0 20 Max Units ns ns ns ns ns ns
TIMING CHARACTERISTICS
Parameter t70 t71 t72 t73 t74 t75 Comment (see Figure 19) ASCLK period ASOFS setup time before ASCLK high ASOFS hold time after ASCLK high ASDI setup time before clock low ASDI hold time after clock low ASDO delay after clock high
t70 ASCLK (O) t71 ASOFS (O) t73 ASDI (i) t74 D9 D8 t75 ASDO (O) D9 D8 D7 A2 A1 A0 D7 A2 A1 A0 t72
Figure 19. EVBC Interface ASPORT Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
EVBC Interface BSPORT
Min 76.9 4 7 4 7 15 0 15 Typ Max Units ns ns ns ns ns ns
TIMING CHARACTERISTICS
Parameter t80 t81 t82 t83 t84 t85 t86 Comment (see Figure 20) BSCLK period BSIFS setup time before BSCLK low BSIFS hold time after BSCLK low BSDI setup time before BSCLK low BSDI hold time after BSCLK low BSOFS delay after BSCLK high BSDO delay after BSCLK high
t80 BSCLK (I) t81 BSIFS (I) t83 t84 BSDI (I) D15 D14 t85 BSOFS (O) t86 BSDO (O)
Figure 20. EVBC Interface BSPORT Timing
t82
D15
D14
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
EVBC Interface VSPORT
Min 76.9 4 7 4 7 0 15 Typ Max Units ns ns ns ns ns ns
TIMING CHARACTERISTICS
Parameter t90 t91 t92 t93 t94 t95 Comment (see Figure 21) VSCLK period VSFS setup time before VSCLK low VSFS hold time after VSCLK low VSDI setup time before VSCLK low VSDI hold time after VSCLK low VSDO delay after VSCLK high
t90 VSCLK (I) t91 VSFS (I) t93 VSDI (I) D15 t94 D14 t95 VSDO (O) D15 D14 D13 t92
Figure 21. EVBC Interface VSPORT Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Parallel Display Interface
Min 462 462 77 Typ Max Units ns ns ns
TIMING CHARACTERISTICS
Parameter t100 t101 t102 Comments (see Figure 22) LCD Control low width (6 CLKIN cycles) LCD Control high width (6 CLKIN cycles) LCD Control high width read extension (1 CLKIN cycle)
ADD 19:O
DISPLAYCS
RD or HWR
t100
LCDCTL
t101
t102
Figure 22. Parallel Display Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426
Serial Display Interface
Min Typ t1*8 or t1*16 0.25 *t103+ 5 5 0.25 *t103 0.25 *t103- 5 Max Units ns ns ns ns ns
TIMING CHARACTERISTICS
Parameter t103 t104 t105 t106 t107 Comment (see Figure 23) DISP_CLK Period DISP_CS Low to Data Valid DISP_CLK Low to Data Valid DISP_CLK Low to DISP_CS high Data Valid to DISP_CLK High
t103
DISP_CLK DISP_D0
t104 t107
D7
t105
D6
// // //
D0
t106
DISP_CS
DISP_A0
Figure 23. Serial Display Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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PACKAGING LQFP Pin Locations
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name USCRI (MONCLK) USCRX (MONRX) USCTX (MONTX) USCCTS (ADD20) USCRTS (GPIO9) GPO10 (GPIO8) ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 GND VDD ADD10 ADD9 BOOTCODE (GND) ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 RAMCS GND VDD ROMCS DATA15 DATA14 DATA13 # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name DATA12 DATA11 DATA10 DATA9 DATA8 RD GND VDD UBS (HWR) LBS (LWR) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND VDD FLASHPWD WR (GPIO2) GND VDD GPIO1 GPIO0 SIMSUPPLY SIMPROG SIMRESET SIMDATAIP SIMDATAOP SIMCLK SIMCARD TCK TMS TDO # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name TDI JTAGEN EEPROMEN EEPROMCLK EEPROMDATA GND VDD VSDO VSFS VSDI VSCLK VBCRESET RXON CLKOUT BSDO BSOFS BSIFS BSDI BSCLK ASCLK ASDI ASOFS ASDO TXPHASE GPIO2 (CPPWD) VDD (GND) GND (VDD) OSCIN (SAMCS) OSCOUT (CPFS) VDDRTC (CPDO) PWRON (CPDI) SYNTHEN1 SYNTHEN0 SYNTHDATA SYNTHCLK AGCA # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name AGCB TXPA
AD6426
CALIBRATERADIO RADIOPWRCTL TXENABLE GND CLKIN VDD GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 LCDCTL DISPLAYCS BACKLIGHT VDD GND OSC13MON (GPPWRCTL) GPCS KEYPADCOL3 KEYPADCOL2 KEYPADCOL1 KEYPADCOL0 GND KEYPADROW5 KEYPADROW4 KEYPADROW3 KEYPADROW2 KEYPADROW1 KEYPADROW0 VDD RESET IRQ6 GPIO8 (BOOTCODE) GPIO9 (H8MODE)
Note: pin names in ( ) are the AD6422 pin names from the AD20msp415 chipset.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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PBGA Pin Locations
# A1 A2 A3 A4 A5 A6 A7 A8 A9 IRQ6 KEYPADROW0 KEYPADROW4 KEYPADCOL1 GPCS VDD VDD CLKIN Pin Name USCR1 # D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Pin Name ADD16 ADD17 USCCTS GPIO8 VDD GND BACKLIGHT GPIO5 SYNTHCLK PWRON OSCOUT VDD ADD13 ADD12 ADD18 ADD15 ADD19 KEYPADROW3 KEYPADCOL3 LCDCTL SYNTHEN1 TXPHASE GND ASDO VDD ADD10 ADD14 GND ADD8 DISPLAYCS BSDO VDDRTC GPIO2 BSCLK ASOFS ASCLK # G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Pin Name BOOTCODE ADD7 ADD9 ADD4 ADD1 ADD11 DATA3 ASDI BSOFS VBCRESET BSDI BSIFS ADD6 ADD3 ADD5 VDD GND FLASHPWD SIMPROG VDD VSCLK VSDO CLKOUT RXON ADD2 RAMCS ADD0 DATA14 DATA7 DATA2 GPIO1 SIMCLK TMS EEPROMCLK VSFS VSDI # K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
AD6426
Pin Name GND ROMCS DATA10 DATA9 VDD DATA6 GND VDD SIMRESET EEPROMEN EEPROMDATA GND DATA15 DATA13 DATA8 UBS DATA4 DATA0 WR GPIO0 SIMDATAIP SIMCARD TDO JTAGEN DATA12 DATA11 RD LWR DATA5 DATA1 VDD GND SIMSUPPLY SIMDATAOP TCK TDI
A10 GND A11 TXPA A12 AGCB B1 B2 B3 B4 B5 B6 B7 B8 B9 USCRX GPIO9 RESET KEYPADROW1 KEYPADROW5 KEYPADCOL2 GND GPIO3 GPIO7
B10 TXENABLE B11 AGCA B12 SYNTHDATA C1 C2 C3 C4 C5 C6 C7 C8 C9 GPIO10 USCRTS USCTX KEYPADROW2 KEYPADCOL0 OSC13MON GPIO4 GPIO6 RADIOPWRCTL
C10 CALIBRATERADIO C11 SYNTHEN0 C12 OSCIN
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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GPIO9 GPIO8 IRQ6 RESET VDD KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 GND KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 GPCS OSC13MON GND VDD BACKLIGHT DISPLAYCS LCDCTL GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VDD CLKIN GND TXENABLE RADIOPWRCTL CALIBRATERADIO TXPA AGCB
AD6426
144 1 USCRI USCRX USCTX USCCTS USCRTS GPIO10 ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 GND VDD ADD10 ADD9 BOOTCODE ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 RAMCS GND VDD ROMCS DATA15 DATA14 DATA13 36 37
109 108 AGCA SYNTHCLK SYNTHDATA SYNTHEN0 SYNTHEN1 PWRON VDDRTC OSCOUT OSCIN GND VDD GPIO2 TXPHASE ASDO ASOFS ASDI ASCLK BSCLK BSDI BSIFS BSOFS BSDO CLKOUT RXON VBCRESET VSCLK VSDI VSFS VSDO VDD GND EEPROMDATA EEPROMCLK EEPROMEN JTAGEN TDI 73 72 DATA12 DATA11 DATA10 DATA9 DATA8 RD GND VDD UBS LBS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND VDD FLASHPWD WR GND VDD GPIO1 GPIO0 SIMSUPPLY SIMPROG SIMRESET SIMDATAIP SIMDATAOP SIMCLK SIMCARD TCK TMS TDO
AD6426
TOP VIEW (PINS DOWN)
Figure 24: LQFP Pin Locations
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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LQFP Outline Dimensions
D D1
AD6426
A
L
1
144
109 108
TQFP 144
TOP VIEW (PINS DOWN)
E1 E
A1 A2
36 37 72
73
e
B
DIM A A1 A2 D, E D1 , E1 L e B C
MILLIMETERS MIN TYP MAX 0.05 1.35 21.80 19.90 0.5 0.17 1.60 0.15 1.45 22.20 20.10 0.75 0.27 0.08
MIN 0.002 0.053 0.858 0.783 0.019 0.007
INCHES TYP
MAX 0.063 0.006 0.057 0.874 0.791 0.030 0.011 0.003
1.40 22.00 20.00 0.6 0.50 0.22
0.055 0.866 0.787 0.024 0.020 0.009
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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PBGA Outline Dimensions
D D2 e
AD6426
12 11 10 9 8 7 6 5 4 3 2
1 A B C D E F G H J K L M
AD6426
E2 E E1
TOP VIEW (Pins Down)
e D1
b
0.10
// ccc C
-Caaa C
// ccc C
A2 c
A1 A
DIM A A1 A2 D D1 D2 E E1 E2 b c e aaa bbb ccc
MIN 1.42 0.30 0.75 12.85 9.95 12.85 9.95 0.45 0.27
MILLIMETERS TYP MAX 1.65 0.40 0.90 13.00 11.00 BSC 10.75 13.00 11.00 BSC 10.75 0.55 0.35 1.00 BSC 1.80 0.50 0.97 13.15 11.55 13.15 11.55 0.65 0.43 0.15 0.20 0.25
MIN 0.05591 0.01181 0.02953 0.50590 0.39173 0.50591 0.39173 0.17716 0.01063
INCHES TYP 0.06496 0.01575 0.03543 0.51181 0.43307 BSC 0.42323 0.51181 0.43307 BSC 0.42323 0.02165 0.01378 0.03937 BSC
MAX 0.07087 0.01968 0.03819 0.51772 0.45472 0.51772 0.45472 0.02559 0.01693 0.00591 0.00787 0.00984
NOTE: 1. BSC - Between Spacing Centers
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD6426 Data Sheet Change Summary
AD6426 Preliminary Revision 2.3
(Changes from Revision 1.0)
Number 1 2 3 4 5 Date 5/19/98 5/19/98 5/19/98 5/19/98 5/19/98 Description of Change Motorola Serial Display mode added. TXENABLE NMI function freeing up the IRQ6 pin added. Dimensional tolerances for BGA package outline drawing added. Memory I/F timing specs separated into characteristics and requirements. Dual band control signals renamed- BANDSELECT0 is multiplexed with GPIO[2], BANDSELECT1 is multiplexed with GPIO[1]. For DB radios requiring a single Bandselect bit, BANDSELECT0 is enabled. For DB radios requiring 2 Bandselect bits then both BANSELECT0,1 can be enabled. These signals were previously referred to as BANDSELECT and DCSSEL. VBC and radio I/F diagram in Figure 6 updated to show a generic DB radio I/F. DAI I/F Pins updated to be consistent with DAI Box users manual. GPIO[7:0] Pin functions in Mode D (Table 24) were incorrectly listed as being all Tristate outputs. The correct function is GPIO7 = TRI and GPIO[6:0] = O. Requirements for 32kHz crystal for slow clocking added. Pin functions in Emulation mode GPO 0,6,7 in Table 24 are renamed to reserve. Memory Interface Timing Specification: read timing specs changed to max with the exception of Control Processor data hold and Parameters broken out separately into requirements and characteristics. In Fig 24 the following pins were incorrectly labeled and thus changed; a) Pin 45 from HWR to UBS b) Pin 46 from LWR to LBS c) Pin 98 from GND to VDD d) Pin 99 from VDD to GND
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6/9/98
June 10, 1998
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AD6426 Data Sheet Change Summary
AD6426 Preliminary Revision 1.0
(Changes from Revision 0.1)
Number 1 2 3 4 5 6 7 Date 1/15/98 1/15/98 1/15/98 1/15/96 1/15/98 1/15/98 1/15/98 Description of Change Dallas I/F added to Feature list. Dallas I/F enable bit polarity changed from logic 1 to 0. Dual Band control section added describing BANDSELECT and DCSSEL signals. Serial Display Interface Timing Characteristics and Diagram added as Figure 23. General Description: F7.2 data services deleted, this is not supported on the EGSMP. General Description: AD6421/25 interfaces to the EGSMP. Serial Display Reset signal removed from Figure 2. Display driver chip reset input is connected to the AD6425 VBC Reset Input and both are driven by the AD6426 VBC reset output. Pin Functionality: VBCRESET added note, also used for Display Reset. Pin Functionality: GPIO1 added note, alternate function DCS_ON. CC Control Registers: Interrupt counter (Addr. 48) changed from 7 to 8 bits. SIM Interface timing characteristics deleted - SIM signals are completely asynchronous with respect to SIMCLK. Plastic Ball Grid Array (PBGA) Package pinout and outline drawing added. EVBC and radio Interface block diagram in Figure 6 updated with dual band control signals. VCLKIN, Clock Input Voltage for ac-coupled sine wave input changed from 100 mVPP to 250 mVPP. Added scan registers USCRX (O), USCRXEN (B), and VSDOEN (T) Corrected output polarity in Notes to active-low (0=output). Added H8 Control registers and register contents in Tables 3 and 4. Buffered UART Register Contents added in Table 5. IIH, IIL Input Current spec min -10, max 10 A added. IIH, IIL Input Current spec min -10, max 10 A added. IOZL, Low Level Output 3-State Leakage Current min 10, max 10 A IOZH, High Level Output 3-State Leakage Current min 10, max 10 A. Absolute Max ratings broken out separately for PBGA package. Control Processor Data setup time changed from 10 to 68 ns. Radio interface section: a reference to the TTP/Hitachi radios added "AD6426 Radio Interface supports radio architectures based on Siemens, Philips, and TTP/Hitachi RF chipsets". Pin Functionality: OSC13MON pin moved from RTC section to general section. Memory interface timing diagram replaced with one used in 6422 data sheet. CC register 46 bits 4-7 SIMCLOCK Polarity, SIMCLOCK off. SIMCLOCK Control, STBYCLKON removed no longer used on 6426. CC registers 80-87 slow clocking control removed from Table 1 & 2 per TTP's request. Peripheral registers 83, 106-109 removed from Table 3 & 4 per TTP's request. All Buffered UART registers removed per TTP's request.
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June 10, 1998
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